From patchwork Wed Oct 26 09:48:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tnhuynh@apm.com X-Patchwork-Id: 686961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t3lbR4RDZz9s2G for ; Wed, 26 Oct 2016 20:49:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=apm.com header.i=@apm.com header.b=Pr28MeL1; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754105AbcJZJsq (ORCPT ); Wed, 26 Oct 2016 05:48:46 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:34875 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754096AbcJZJsp (ORCPT ); Wed, 26 Oct 2016 05:48:45 -0400 Received: by mail-pf0-f181.google.com with SMTP id s8so137153163pfj.2 for ; Wed, 26 Oct 2016 02:48:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apm.com; s=apm; h=from:to:cc:subject:date:message-id; bh=6QjdaIe3i2R7caNWozrIeSKow4ungDlYh9d80mC/kaM=; b=Pr28MeL1oYciq5whJkOTpVI/mNitdwvWE/1SeOWiIXNQcN9XVrI7FSaoIdU0N3Xqy1 05Uv38WI/BltCaq7je+EmPZxPGs2kVN6SbSxtBe0o8y1fWBT8hrSnEFvPmGWcVeujGOl qQZw3a1TtHZ/jlMjB64S0ajY5za8C9B+88BzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6QjdaIe3i2R7caNWozrIeSKow4ungDlYh9d80mC/kaM=; b=d9vofsp84SKvAu4s66Q+vp60pQOWMq5KPi6RPKSEKnQrzE1hmmtgQ2KI4fm+PCKFlf wwBQY4r40Ex/O2p2cowGoOicuRwY2666fyvLL/86VVp612f14BIYtcNnpIe4FszztHtD KkG86c67ItDsLS4bTR6LVpArOU0VSiVgzRz8fSuwFegbWuUdJfiOEcihwXBrZ94Q3D9R PM97I0zGsSEDRBYtnH1JONvnNLjRxCOnmeydDNglzW9lJvAqny8NLsEov9LztxxOGjU2 f4V6fJ3k/7SKfiToeMnY55imv93I8yoU/t31EDG2V+873HeNq93hxLQJyEzwACFqUOc2 S7ig== X-Gm-Message-State: ABUngvdrNWn0aHbmizO6sK2uJGMYDz+W47dmO/DmsQi2XDevYcNrGdPns1LukKJLRfnijE1j X-Received: by 10.99.52.75 with SMTP id b72mr2191366pga.42.1477475324646; Wed, 26 Oct 2016 02:48:44 -0700 (PDT) Received: from localhost.localdomain ([118.69.219.197]) by smtp.gmail.com with ESMTPSA id xv9sm2841693pab.36.2016.10.26.02.48.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Oct 2016 02:48:43 -0700 (PDT) From: tnhuynh@apm.com To: Jarkko Nikula , Andy Shevchenko , Mika Westerberg , Wolfram Sang , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Loc Ho , Thang Nguyen , Phong Vo , patches@apm.com, Tin Huynh Subject: [PATCH v2] I2C Designware Core Supports SMBUS BLOCK Date: Wed, 26 Oct 2016 16:48:28 +0700 Message-Id: <1477475308-24293-1-git-send-email-tnhuynh@apm.com> X-Mailer: git-send-email 1.7.1 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Tin Huynh Free and Open IPMI use SMBUS BLOCK Read/Write to support SSIF protocol. However, I2C Designwave Core Driver doesn't handle the case at the moment. The below patch supports this feature. Change from V1: -Remove empty lines -Add flags variable to make clean code -Change DW_DEFAULT_FUNCTIONALITY in i2c-designware-pcidrv.c Signed-off-by: Tin Huynh --- drivers/i2c/busses/i2c-designware-core.c | 36 ++++++++++++++++++++++++-- drivers/i2c/busses/i2c-designware-pcidrv.c | 1 + drivers/i2c/busses/i2c-designware-platdrv.c | 1 + 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c index 1fe93c4..c77a83f 100644 --- a/drivers/i2c/busses/i2c-designware-core.c +++ b/drivers/i2c/busses/i2c-designware-core.c @@ -543,6 +543,7 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) intr_mask = DW_IC_INTR_DEFAULT_MASK; for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { + u32 flags = msgs[dev->msg_write_idx].flags; /* * if target address has changed, we need to * reprogram the target address in the i2c @@ -588,8 +589,15 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) * detected from the registers so we set it always * when writing/reading the last byte. */ + + /* + * i2c-core.c always set the buffer length of + * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will + * be adjusted when receiving the first byte. + * Thus we can't stop the transaction here. + */ if (dev->msg_write_idx == dev->msgs_num - 1 && - buf_len == 1) + buf_len == 1 && !(flags & I2C_M_RECV_LEN)) cmd |= BIT(9); if (need_restart) { @@ -614,7 +622,12 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) dev->tx_buf = buf; dev->tx_buf_len = buf_len; - if (buf_len > 0) { + /* + * Because we don't know the buffer length in the + * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop + * the transaction here. + */ + if (buf_len > 0 || flags & I2C_M_RECV_LEN) { /* more bytes to be written */ dev->status |= STATUS_WRITE_IN_PROGRESS; break; @@ -659,7 +672,24 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) rx_valid = dw_readl(dev, DW_IC_RXFLR); for (; len > 0 && rx_valid > 0; len--, rx_valid--) { - *buf++ = dw_readl(dev, DW_IC_DATA_CMD); + u32 flags = msgs[dev->msg_read_idx].flags; + *buf = dw_readl(dev, DW_IC_DATA_CMD); + /* ensure length byte is a valid value */ + if (flags & I2C_M_RECV_LEN && + *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) { + /* + * Adjust the buffer length and mask the flag + * after receiving the first byte + */ + len = (flags & I2C_CLIENT_PEC) ? + *buf + 2 : *buf + 1; + dev->tx_buf_len = len > dev->rx_outstanding ? + len - dev->rx_outstanding : 0; + msgs[dev->msg_read_idx].len = len; + flags &= ~I2C_M_RECV_LEN; + msgs[dev->msg_read_idx].flags = flags; + } + buf++; dev->rx_outstanding--; } diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c index 96f8230..8ffe2da 100644 --- a/drivers/i2c/busses/i2c-designware-pcidrv.c +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c @@ -75,6 +75,7 @@ struct dw_pci_controller { I2C_FUNC_SMBUS_BYTE | \ I2C_FUNC_SMBUS_BYTE_DATA | \ I2C_FUNC_SMBUS_WORD_DATA | \ + I2C_FUNC_SMBUS_BLOCK_DATA | \ I2C_FUNC_SMBUS_I2C_BLOCK) /* Merrifield HCNT/LCNT/SDA hold time */ diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index 0b42a12..886fb62 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -220,6 +220,7 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_I2C_BLOCK; dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |