@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config ARCH_LS1046A
bool
@@ -23,6 +24,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config ARCH_LS2080A
bool
@@ -33,6 +35,7 @@ config ARCH_LS2080A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A009798
config FSL_LSCH2
bool
@@ -59,6 +62,9 @@ config SYS_FSL_ERRATUM_A010539
config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
+config SYS_FSL_ERRATUM_A009798
+ bool "Workaround for USB PHY erratum A009798"
+
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
@@ -49,6 +49,25 @@ static void erratum_a009008(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
}
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+ val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+ val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+ scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -215,6 +234,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+ erratum_a009798();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -392,6 +412,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+ erratum_a009798();
}
#endif
@@ -340,6 +340,7 @@ struct ccsr_gur {
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
@@ -135,6 +135,7 @@
#define SCFG_USB3PRM1CR 0x000
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */