diff mbox

S/390: Add support for arch<n> arch/tune options.

Message ID 20161021140255.10971-1-krebbel@linux.vnet.ibm.com
State New
Headers show

Commit Message

Andreas Krebbel Oct. 21, 2016, 2:02 p.m. UTC 
This patch adds an alternate CPU level naming following the
architecture level number in the Principles of Operations manual.  So
instead of having z196, zEC12, and z13 you can use arch9, arch10, and
arch11.  The old cpu names stay valid and should preferably be used.

The alternate names are supposed to improve compatibility with the IBM
XL compiler toolchain which uses the arch numbering.

Tested on s390x. No regression.

I'll commit it in a few days.

-Andreas-

gcc/testsuite/ChangeLog:

2016-10-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gcc.target/s390/target-attribute/tattr-m64-33.c: New test.

gcc/ChangeLog:

2016-10-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* config/s390/s390.opt: Support alternate cpu level naming (archXX).
	* config.gcc: Support alternate archXX cpu levels with
	--with-arch= and --with-tune=.
	* config/s390/linux.h: Translate new archXX cpu levels to the
	original names when calling GAS.
	* config/s390/tpf.h: Likewise.
	* doc/invoke.texi: Document the alternate cpu level names.
---
 gcc/config.gcc                                     |   2 +-
 gcc/config/s390/linux.h                            |  14 +-
 gcc/config/s390/s390.opt                           |  24 ++
 gcc/config/s390/tpf.h                              |  17 +-
 gcc/doc/invoke.texi                                |  16 +-
 .../s390/target-attribute/tattr-m64-33.c           | 353 +++++++++++++++++++++
 6 files changed, 416 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/s390/target-attribute/tattr-m64-33.c
diff mbox

Patch

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2143d63..507af5c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4172,7 +4172,7 @@  case "${target}" in
 		for which in arch tune; do
 			eval "val=\$with_$which"
 			case ${val} in
-			"" | native | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13)
+			"" | native | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13 | arch3 | arch5 | arch6 | arch7 | arch8 | arch9 | arch10 | arch11)
 				# OK
 				;;
 			*)
diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h
index 9b00af7..541006d 100644
--- a/gcc/config/s390/linux.h
+++ b/gcc/config/s390/linux.h
@@ -47,9 +47,19 @@  along with GCC; see the file COPYING3.  If not see
 
 
 /* Target specific assembler settings.  */
-
+/* Rewrite -march=arch* options to the original CPU name in order to
+   make it work with older binutils.  */
 #undef  ASM_SPEC
-#define ASM_SPEC "%{m31&m64}%{mesa&mzarch}%{march=*}"
+#define ASM_SPEC					\
+  "%{m31&m64}%{mesa&mzarch}%{march=z*}"			\
+  "%{march=arch3:-march=g5}"				\
+  "%{march=arch5:-march=z900}"				\
+  "%{march=arch6:-march=z990}"				\
+  "%{march=arch7:-march=z9-ec}"				\
+  "%{march=arch8:-march=z10}"				\
+  "%{march=arch9:-march=z196}"				\
+  "%{march=arch10:-march=zEC12}"			\
+  "%{march=arch11:-march=z13}"
 
 
 /* Target specific linker settings.  */
diff --git a/gcc/config/s390/s390.opt b/gcc/config/s390/s390.opt
index 1ae1396..569ed95 100644
--- a/gcc/config/s390/s390.opt
+++ b/gcc/config/s390/s390.opt
@@ -62,33 +62,57 @@  EnumValue
 Enum(processor_type) String(g5) Value(PROCESSOR_9672_G5)
 
 EnumValue
+Enum(processor_type) String(arch3) Value(PROCESSOR_9672_G5)
+
+EnumValue
 Enum(processor_type) String(g6) Value(PROCESSOR_9672_G6)
 
 EnumValue
 Enum(processor_type) String(z900) Value(PROCESSOR_2064_Z900)
 
 EnumValue
+Enum(processor_type) String(arch5) Value(PROCESSOR_2064_Z900)
+
+EnumValue
 Enum(processor_type) String(z990) Value(PROCESSOR_2084_Z990)
 
 EnumValue
+Enum(processor_type) String(arch6) Value(PROCESSOR_2084_Z990)
+
+EnumValue
 Enum(processor_type) String(z9-109) Value(PROCESSOR_2094_Z9_109)
 
 EnumValue
 Enum(processor_type) String(z9-ec) Value(PROCESSOR_2094_Z9_EC)
 
 EnumValue
+Enum(processor_type) String(arch7) Value(PROCESSOR_2094_Z9_EC)
+
+EnumValue
 Enum(processor_type) String(z10) Value(PROCESSOR_2097_Z10)
 
 EnumValue
+Enum(processor_type) String(arch8) Value(PROCESSOR_2097_Z10)
+
+EnumValue
 Enum(processor_type) String(z196) Value(PROCESSOR_2817_Z196)
 
 EnumValue
+Enum(processor_type) String(arch9) Value(PROCESSOR_2817_Z196)
+
+EnumValue
 Enum(processor_type) String(zEC12) Value(PROCESSOR_2827_ZEC12)
 
 EnumValue
+Enum(processor_type) String(arch10) Value(PROCESSOR_2827_ZEC12)
+
+EnumValue
 Enum(processor_type) String(z13) Value(PROCESSOR_2964_Z13)
 
 EnumValue
+Enum(processor_type) String(arch11) Value(PROCESSOR_2964_Z13)
+
+EnumValue
 Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
 
 mbackchain
diff --git a/gcc/config/s390/tpf.h b/gcc/config/s390/tpf.h
index f794c68..a5423a6 100644
--- a/gcc/config/s390/tpf.h
+++ b/gcc/config/s390/tpf.h
@@ -90,9 +90,20 @@  along with GCC; see the file COPYING3.  If not see
 #undef CPLUSPLUS_CPP_SPEC
 #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
 
-#undef ASM_SPEC
-#define ASM_SPEC "%{m31&m64}%{mesa&mzarch}%{march=*} \
-                  -alshd=%b.lst"
+/* Rewrite -march=arch* options to the original CPU name in order to
+   make it work with older binutils.  */
+#undef  ASM_SPEC
+#define ASM_SPEC					\
+  "%{m31&m64}%{mesa&mzarch}%{march=z*}"			\
+  "%{march=arch3:-march=g5}"				\
+  "%{march=arch5:-march=z900}"				\
+  "%{march=arch6:-march=z990}"				\
+  "%{march=arch7:-march=z9-ec}"				\
+  "%{march=arch8:-march=z10}"				\
+  "%{march=arch9:-march=z196}"				\
+  "%{march=arch10:-march=zEC12}"			\
+  "%{march=arch11:-march=z13}"				\
+  " -alshd=%b.lst"
 
 #undef LIB_SPEC
 #define LIB_SPEC "-lCTIS -lCISO -lCLBM -lCTAL -lCFVS -lCTBX -lCTXO \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0241cb5..8a03c85 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22109,10 +22109,18 @@  The default is to not print debug information.
 @opindex march
 Generate code that runs on @var{cpu-type}, which is the name of a
 system representing a certain processor type.  Possible values for
-@var{cpu-type} are @samp{z900}, @samp{z990}, @samp{z9-109},
-@samp{z9-ec}, @samp{z10}, @samp{z196}, @samp{zEC12}, and @samp{z13}.
-The default is @option{-march=z900}.  @samp{g5} and @samp{g6} are
-deprecated and will be removed with future releases.
+@var{cpu-type} are @samp{z900}/@samp{arch5}, @samp{z990}/@samp{arch6},
+@samp{z9-109}, @samp{z9-ec}/@samp{arch7}, @samp{z10}/@samp{arch8},
+@samp{z196}/@samp{arch9}, @samp{zEC12}, @samp{z13}/@samp{arch11}, and
+@samp{native}.
+
+The default is @option{-march=z900}.  @samp{g5}/@samp{arch3} and
+@samp{g6} are deprecated and will be removed with future releases.
+
+Specifying @samp{native} as cpu type can be used to select the best
+architecture option for the host processor.
+@option{-march=native} has no effect if GCC does not recognize the
+processor.
 
 @item -mtune=@var{cpu-type}
 @opindex mtune
diff --git a/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m64-33.c b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m64-33.c
new file mode 100644
index 0000000..5476ad3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/target-attribute/tattr-m64-33.c
@@ -0,0 +1,353 @@ 
+/* Functional tests for the "target" attribute and pragma.  */
+
+/* { dg-do assemble { target { lp64 } } } */
+/* { dg-require-effective-target target_attribute } */
+/* { dg-options "-save-temps -mdebug -m64 -march=arch11 -mtune=arch8 -mstack-size=4096 -mstack-guard=0 -mbranch-cost=2 -mwarn-framesize=0 -mhard-dfp -mno-backchain -mhard-float -mno-vx -mhtm -mpacked-stack -mno-small-exec -mzvector -mno-mvcle -mzarch -mwarn-dynamicstack" } */
+
+/**
+ **
+ ** Start
+ **
+ **/
+
+void fn_default_start (void) { }
+/* { dg-final { scan-assembler "fn:fn_default_start ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start se0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_start wd1" } } */
+
+/**
+ **
+ ** Attribute
+ **
+ **/
+
+__attribute__ ((target ("arch=arch11")))
+void fn_att_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_att_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1 wd1" } } */
+
+void fn_att_1_default (void) { }
+
+__attribute__ ((target ("arch=arch8")))
+void fn_att_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_att_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0 wd1" } } */
+
+void fn_att_0_default (void) { }
+
+__attribute__ ((target ("arch=arch8,arch=arch11")))
+void fn_att_0_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_att_0_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_0_1 wd1" } } */
+
+__attribute__ ((target ("arch=arch11,arch=arch8")))
+void fn_att_1_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_att_1_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_att_1_0 wd1" } } */
+
+/**
+ **
+ ** Pragma
+ **
+ **/
+
+#pragma GCC target ("arch=arch11")
+void fn_pragma_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1 wd1" } } */
+#pragma GCC reset_options
+
+void fn_pragma_1_default (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_default wd1" } } */
+
+#pragma GCC target ("arch=arch8")
+void fn_pragma_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0 wd1" } } */
+#pragma GCC reset_options
+
+void fn_pragma_0_default (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_default wd1" } } */
+
+#pragma GCC target ("arch=arch8")
+#pragma GCC target ("arch=arch11")
+void fn_pragma_0_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_1 wd1" } } */
+#pragma GCC reset_options
+
+#pragma GCC target ("arch=arch11")
+#pragma GCC target ("arch=arch8")
+void fn_pragma_1_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_0 wd1" } } */
+#pragma GCC reset_options
+
+/**
+ **
+ ** Pragma and attribute
+ **
+ **/
+
+#pragma GCC target ("arch=arch11")
+__attribute__ ((target ("arch=arch11")))
+void fn_pragma_1_att_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_1 wd1" } } */
+#pragma GCC reset_options
+
+#pragma GCC target ("arch=arch11")
+__attribute__ ((target ("arch=arch11")))
+void fn_pragma_0_att_1 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_1 wd1" } } */
+#pragma GCC reset_options
+
+#pragma GCC target ("arch=arch11")
+__attribute__ ((target ("arch=arch8")))
+void fn_pragma_1_att_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_1_att_0 wd1" } } */
+#pragma GCC reset_options
+
+#pragma GCC target ("arch=arch11")
+__attribute__ ((target ("arch=arch8")))
+void fn_pragma_0_att_0 (void) { }
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ar6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 se0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_pragma_0_att_0 wd1" } } */
+#pragma GCC reset_options
+
+/**
+ **
+ ** End
+ **
+ **/
+
+void fn_default_end (void) { }
+/* { dg-final { scan-assembler "fn:fn_default_end ar9" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end tu6" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end ss4096" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end sg0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end bc2" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end wf0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end hd1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end ba0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end hf1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end vx0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end ht1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end ps1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end se0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end zv1" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end mv0" } } */
+/* { dg-final { scan-assembler "fn:fn_default_end wd1" } } */