From patchwork Wed Oct 20 09:04:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68414 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 25C28B6EDF for ; Wed, 20 Oct 2010 20:37:13 +1100 (EST) Received: from localhost ([127.0.0.1]:44512 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8UlZ-0006Bj-80 for incoming@patchwork.ozlabs.org; Wed, 20 Oct 2010 05:15:25 -0400 Received: from [140.186.70.92] (port=42726 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8UbN-0002l4-JN for qemu-devel@nongnu.org; Wed, 20 Oct 2010 05:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P8UbM-0007rV-H0 for qemu-devel@nongnu.org; Wed, 20 Oct 2010 05:04:53 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:50600) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P8UbM-0007rA-2U for qemu-devel@nongnu.org; Wed, 20 Oct 2010 05:04:52 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 8C31887384; Wed, 20 Oct 2010 18:04:49 +0900 (JST) Received: (nullmailer pid 20982 invoked by uid 1000); Wed, 20 Oct 2010 09:04:49 -0000 Date: Wed, 20 Oct 2010 18:04:49 +0900 From: Isaku Yamahata To: "Michael S\. Tsirkin" Message-ID: <20101020090449.GA20484@valinux.co.jp> References: <6490a259eb9ff0b787998f465cdc0bec92daceb2.1287562197.git.yamahata@valinux.co.jp> <20101020084920.GB10783@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20101020084920.GB10783@redhat.com> User-Agent: Mutt/1.5.19 (2009-01-05) X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com Subject: [Qemu-devel] Re: [PATCH v6 02/12] pci/bridge: fix pci_bridge_reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Wed, Oct 20, 2010 at 10:49:20AM +0200, Michael S. Tsirkin wrote: > On Wed, Oct 20, 2010 at 05:18:51PM +0900, Isaku Yamahata wrote: > > The default value of base/limit registers aren't specified in the spec. > > So pci_bridge_reset() shouldn't touch them. > > Instead, introduced two functions to reset those registers in a way > > of typical implementation. zero base/limit registers or disable forwarding. > > They will be used later. > > > > Signed-off-by: Isaku Yamahata > > The commit message seems to be out of date? Oops. Here's the update one. Only the commit log change. Should I resend the whole series? From a3e0fd4d19879156d40f87228d09c660fc512b16 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Isaku Yamahata Date: Fri, 15 Oct 2010 19:33:50 +0900 Subject: [PATCH v6 02/12] pci/bridge: fix pci_bridge_reset() The lower bits of base/limit registers is RO and shouldn't be zero cleared on reset. This patch fixes it. In fact, the default value of base/limit registers aren't specified in the spec. And some bridges disable forwarding on reset instead of zeroing base/limit registers. So introduce one function to disable bridge forwarding so that such bridges can use it. It will be used later. Signed-off-by: Isaku Yamahata --- Changes v5 -> v6: - pci_bridge_disable_base_limit() Changes v4 -> v5: - drop the lines in pci_bridge_reset() - introduced two functions to reset base/limit registers. --- hw/pci_bridge.c | 48 ++++++++++++++++++++++++++++++++++++++++++------ hw/pci_bridge.h | 1 + 2 files changed, 43 insertions(+), 6 deletions(-) diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 638e3b3..7e8488a 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -151,6 +151,26 @@ void pci_bridge_write_config(PCIDevice *d, } } +void pci_bridge_disable_base_limit(PCIDevice *dev) +{ + uint8_t *conf = dev->config; + + pci_byte_test_and_set_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); + pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); + pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); +} + /* reset bridge specific configuration registers */ void pci_bridge_reset_reg(PCIDevice *dev) { @@ -161,12 +181,28 @@ void pci_bridge_reset_reg(PCIDevice *dev) conf[PCI_SUBORDINATE_BUS] = 0; conf[PCI_SEC_LATENCY_TIMER] = 0; - conf[PCI_IO_BASE] = 0; - conf[PCI_IO_LIMIT] = 0; - pci_set_word(conf + PCI_MEMORY_BASE, 0); - pci_set_word(conf + PCI_MEMORY_LIMIT, 0); - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0); - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0); + /* + * the default values for base/limit registers aren't specified + * in the PCI-to-PCI-bridge spec. So we don't thouch them here. + * Each implementation can override it. + * typical implementation does + * zero base/limit registers or + * disable forwarding: pci_bridge_disable_base_limit() + * If disable forwarding is wanted, call pci_bridge_disable_base_limit() + * after this function. + */ + pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h index f6fade0..84411a6 100644 --- a/hw/pci_bridge.h +++ b/hw/pci_bridge.h @@ -39,6 +39,7 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); +void pci_bridge_disable_base_limit(PCIDevice *dev); void pci_bridge_reset_reg(PCIDevice *dev); void pci_bridge_reset(DeviceState *qdev);