Patchwork Re: [PATCH v6 02/12] pci/bridge: fix pci_bridge_reset()

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Submitter Isaku Yamahata
Date Oct. 20, 2010, 9:04 a.m.
Message ID <20101020090449.GA20484@valinux.co.jp>
Download mbox | patch
Permalink /patch/68414/
State New
Headers show

Comments

Isaku Yamahata - Oct. 20, 2010, 9:04 a.m.
On Wed, Oct 20, 2010 at 10:49:20AM +0200, Michael S. Tsirkin wrote:
> On Wed, Oct 20, 2010 at 05:18:51PM +0900, Isaku Yamahata wrote:
> > The default value of base/limit registers aren't specified in the spec.
> > So pci_bridge_reset() shouldn't touch them.
> > Instead, introduced two functions to reset those registers in a way
> > of typical implementation. zero base/limit registers or disable forwarding.
> > They will be used later.
> > 
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> 
> The commit message seems to be out of date?

Oops. Here's the update one. Only the commit log change.
Should I resend the whole series?

From a3e0fd4d19879156d40f87228d09c660fc512b16 Mon Sep 17 00:00:00 2001
Message-Id: <a3e0fd4d19879156d40f87228d09c660fc512b16.1287565438.git.yamahata@valinux.co.jp>
In-Reply-To: <cover.1287565438.git.yamahata@valinux.co.jp>
References: <cover.1287565438.git.yamahata@valinux.co.jp>
From: Isaku Yamahata <yamahata@valinux.co.jp>
Date: Fri, 15 Oct 2010 19:33:50 +0900
Subject: [PATCH v6 02/12] pci/bridge: fix pci_bridge_reset()

The lower bits of base/limit registers is RO and shouldn't be zero cleared
on reset. This patch fixes it.
In fact, the default value of base/limit registers aren't specified
in the spec. And some bridges disable forwarding on reset instead of
zeroing base/limit registers.
So introduce one function to disable bridge forwarding so that
such bridges can use it. It will be used later.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Changes v5 -> v6:
- pci_bridge_disable_base_limit()

Changes v4 -> v5:
- drop the lines in pci_bridge_reset()
- introduced two functions to reset base/limit registers.
---
 hw/pci_bridge.c |   48 ++++++++++++++++++++++++++++++++++++++++++------
 hw/pci_bridge.h |    1 +
 2 files changed, 43 insertions(+), 6 deletions(-)
Michael S. Tsirkin - Oct. 20, 2010, 10 a.m.
On Wed, Oct 20, 2010 at 06:04:49PM +0900, Isaku Yamahata wrote:
> On Wed, Oct 20, 2010 at 10:49:20AM +0200, Michael S. Tsirkin wrote:
> > On Wed, Oct 20, 2010 at 05:18:51PM +0900, Isaku Yamahata wrote:
> > > The default value of base/limit registers aren't specified in the spec.
> > > So pci_bridge_reset() shouldn't touch them.
> > > Instead, introduced two functions to reset those registers in a way
> > > of typical implementation. zero base/limit registers or disable forwarding.
> > > They will be used later.
> > > 
> > > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> > 
> > The commit message seems to be out of date?
> 
> Oops. Here's the update one. Only the commit log change.
> Should I resend the whole series?

No, I can handle that.

Patch

diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index 638e3b3..7e8488a 100644
--- a/hw/pci_bridge.c
+++ b/hw/pci_bridge.c
@@ -151,6 +151,26 @@  void pci_bridge_write_config(PCIDevice *d,
     }
 }
 
+void pci_bridge_disable_base_limit(PCIDevice *dev)
+{
+    uint8_t *conf = dev->config;
+
+    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
+                               PCI_IO_RANGE_MASK & 0xff);
+    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
+                                 PCI_IO_RANGE_MASK & 0xff);
+    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
+                               PCI_MEMORY_RANGE_MASK & 0xffff);
+    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
+                                 PCI_MEMORY_RANGE_MASK & 0xffff);
+    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
+                               PCI_PREF_RANGE_MASK & 0xffff);
+    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
+                                 PCI_PREF_RANGE_MASK & 0xffff);
+    pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
+    pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
+}
+
 /* reset bridge specific configuration registers */
 void pci_bridge_reset_reg(PCIDevice *dev)
 {
@@ -161,12 +181,28 @@  void pci_bridge_reset_reg(PCIDevice *dev)
     conf[PCI_SUBORDINATE_BUS] = 0;
     conf[PCI_SEC_LATENCY_TIMER] = 0;
 
-    conf[PCI_IO_BASE] = 0;
-    conf[PCI_IO_LIMIT] = 0;
-    pci_set_word(conf + PCI_MEMORY_BASE, 0);
-    pci_set_word(conf + PCI_MEMORY_LIMIT, 0);
-    pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0);
-    pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0);
+    /*
+     * the default values for base/limit registers aren't specified
+     * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
+     * Each implementation can override it.
+     * typical implementation does
+     * zero base/limit registers or
+     * disable forwarding: pci_bridge_disable_base_limit()
+     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
+     * after this function.
+     */
+    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
+                                 PCI_IO_RANGE_MASK & 0xff);
+    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
+                                 PCI_IO_RANGE_MASK & 0xff);
+    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
+                                 PCI_MEMORY_RANGE_MASK & 0xffff);
+    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
+                                 PCI_MEMORY_RANGE_MASK & 0xffff);
+    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
+                                 PCI_PREF_RANGE_MASK & 0xffff);
+    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
+                                 PCI_PREF_RANGE_MASK & 0xffff);
     pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
     pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
 
diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h
index f6fade0..84411a6 100644
--- a/hw/pci_bridge.h
+++ b/hw/pci_bridge.h
@@ -39,6 +39,7 @@  pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type);
 
 void pci_bridge_write_config(PCIDevice *d,
                              uint32_t address, uint32_t val, int len);
+void pci_bridge_disable_base_limit(PCIDevice *dev);
 void pci_bridge_reset_reg(PCIDevice *dev);
 void pci_bridge_reset(DeviceState *qdev);