From patchwork Wed Oct 20 08:18:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 112F7B70D2 for ; Wed, 20 Oct 2010 19:28:54 +1100 (EST) Received: from localhost ([127.0.0.1]:54272 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8U25-00086D-26 for incoming@patchwork.ozlabs.org; Wed, 20 Oct 2010 04:28:25 -0400 Received: from [140.186.70.92] (port=43764 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8Tyh-0004An-6H for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:25:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P8Tt4-0000Wv-Of for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:19:09 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:46426) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P8Tt3-0000Vx-Ur for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:19:06 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 01CD88740C; Wed, 20 Oct 2010 17:19:04 +0900 (JST) Received: (nullmailer pid 20052 invoked by uid 1000); Wed, 20 Oct 2010 08:19:01 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Wed, 20 Oct 2010 17:18:54 +0900 Message-Id: <532a16651a0985e5376d3b293faa93af3a52ad2f.1287562197.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v6 05/12] x3130: pcie upstream port X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement TI x3130 pcie upstream port switch. Signed-off-by: Isaku Yamahata --- Changes v5 -> v6: - compilation adjustment. - delete aer bits. Changes v4 -> v5: - remove flr related stuff. This will be addressed at the next phase. - use pci_xxx_test_and_xxx_mask(). Chnages v3 -> v4: - rename pcie_upstream -> x3130_upstream. - compilation adjustment. Changes v2 -> v3: - compilation adjustment. --- Makefile.objs | 2 +- hw/xio3130_upstream.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/xio3130_upstream.h | 10 +++ 3 files changed, 185 insertions(+), 1 deletions(-) create mode 100644 hw/xio3130_upstream.c create mode 100644 hw/xio3130_upstream.h diff --git a/Makefile.objs b/Makefile.objs index 3a05322..b1ef2bb 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -140,7 +140,7 @@ hw-obj-y = hw-obj-y += vl.o loader.o hw-obj-y += virtio.o virtio-console.o hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o pci_bridge.o -hw-obj-y += ioh3420.o +hw-obj-y += ioh3420.o xio3130_upstream.o hw-obj-y += watchdog.o hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o hw-obj-$(CONFIG_ECC) += ecc.o diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c new file mode 100644 index 0000000..d9d637f --- /dev/null +++ b/hw/xio3130_upstream.c @@ -0,0 +1,174 @@ +/* + * xio3130_upstream.c + * TI X3130 pci express upstream port switch + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "pci_ids.h" +#include "msi.h" +#include "pcie.h" +#include "xio3130_upstream.h" + +#define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ +#define XIO3130_REVISION 0x2 +#define XIO3130_MSI_OFFSET 0x70 +#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT +#define XIO3130_MSI_NR_VECTOR 1 +#define XIO3130_SSVID_OFFSET 0x80 +#define XIO3130_SSVID_SVID 0 +#define XIO3130_SSVID_SSID 0 +#define XIO3130_EXP_OFFSET 0x90 +#define XIO3130_AER_OFFSET 0x100 + +static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, + uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + pcie_cap_flr_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + /* TODO: AER */ +} + +static void xio3130_upstream_reset(DeviceState *qdev) +{ + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); + msi_reset(d); + pci_bridge_reset(qdev); + pcie_cap_deverr_reset(d); +} + +static int xio3130_upstream_initfn(PCIDevice *d) +{ + PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); + PCIEPort *p = DO_UPCAST(PCIEPort, br, br); + int rc; + + rc = pci_bridge_initfn(d); + if (rc < 0) { + return rc; + } + + pcie_port_init_reg(d); + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI); + pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130U); + d->config[PCI_REVISION_ID] = XIO3130_REVISION; + + rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, + XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, + XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); + if (rc < 0) { + return rc; + } + rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, + XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); + if (rc < 0) { + return rc; + } + rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, + p->port); + if (rc < 0) { + return rc; + } + + /* TODO: implement FLR */ + pcie_cap_flr_init(d); + + pcie_cap_deverr_init(d); + /* TODO: AER */ + + return 0; +} + +static int xio3130_upstream_exitfn(PCIDevice *d) +{ + /* TODO: AER */ + msi_uninit(d); + pcie_cap_exit(d); + return pci_bridge_exitfn(d); +} + +PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port) +{ + PCIDevice *d; + PCIBridge *br; + DeviceState *qdev; + + d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); + if (!d) { + return NULL; + } + br = DO_UPCAST(PCIBridge, dev, d); + + qdev = &br->dev.qdev; + pci_bridge_map_irq(br, bus_name, map_irq); + qdev_prop_set_uint8(qdev, "port", port); + qdev_init_nofail(qdev); + + return DO_UPCAST(PCIEPort, br, br); +} + +static const VMStateDescription vmstate_xio3130_upstream = { + .name = "xio3130-express-upstream-port", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), + /* TODO: AER */ + VMSTATE_END_OF_LIST() + } +}; + +static PCIDeviceInfo xio3130_upstream_info = { + .qdev.name = "x3130-upstream", + .qdev.desc = "TI X3130 Upstream Port of PCI Express Switch", + .qdev.size = sizeof(PCIEPort), + .qdev.reset = xio3130_upstream_reset, + .qdev.vmsd = &vmstate_xio3130_upstream, + + .is_express = 1, + .is_bridge = 1, + .config_write = xio3130_upstream_write_config, + .init = xio3130_upstream_initfn, + .exit = xio3130_upstream_exitfn, + + .qdev.props = (Property[]) { + DEFINE_PROP_UINT8("port", PCIEPort, port, 0), + /* TODO: AER */ + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void xio3130_upstream_register(void) +{ + pci_qdev_register(&xio3130_upstream_info); +} + +device_init(xio3130_upstream_register); + + +/* + * Local variables: + * c-indent-level: 4 + * c-basic-offset: 4 + * tab-width: 8 + * indent-tab-mode: nil + * End: + */ diff --git a/hw/xio3130_upstream.h b/hw/xio3130_upstream.h new file mode 100644 index 0000000..e996997 --- /dev/null +++ b/hw/xio3130_upstream.h @@ -0,0 +1,10 @@ +#ifndef QEMU_XIO3130_UPSTREAM_H +#define QEMU_XIO3130_UPSTREAM_H + +#include "pcie_port.h" + +PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port); + +#endif /* QEMU_XIO3130_H */