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[v2,08/18] tcg/mips: Implement field extraction opcodes

Message ID 1476803431-7208-9-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson Oct. 18, 2016, 3:10 p.m. UTC 
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/mips/tcg-target.h     | 2 +-
 tcg/mips/tcg-target.inc.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

Comments

Yongbok Kim Oct. 27, 2016, 1:40 p.m. UTC | #1 
On 18/10/2016 16:10, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/mips/tcg-target.h     | 2 +-
>  tcg/mips/tcg-target.inc.c | 4 ++++
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
> index 1bcea3b..f1c3137 100644
> --- a/tcg/mips/tcg-target.h
> +++ b/tcg/mips/tcg-target.h
> @@ -123,7 +123,7 @@ extern bool use_mips32r2_instructions;
>  #define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
>  #define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions
>  #define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
> -#define TCG_TARGET_HAS_extract_i32      0
> +#define TCG_TARGET_HAS_extract_i32      use_mips32r2_instructions
>  #define TCG_TARGET_HAS_sextract_i32     0
>  #define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
>  #define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
> index abce602..192dd49 100644
> --- a/tcg/mips/tcg-target.inc.c
> +++ b/tcg/mips/tcg-target.inc.c
> @@ -1637,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>      case INDEX_op_deposit_i32:
>          tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
>          break;
> +    case INDEX_op_extract_i32:
> +        tcg_out_opc_bf(s, OPC_EXT, a0, a1, a3 + args[3] - 1, a2);

The msbd (5th argument) must be (a2 + args[3] - 1). In fact "a3" isn't defined.

> +        break;
>  
>      case INDEX_op_brcond_i32:
>          tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
> @@ -1736,6 +1739,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
>      { INDEX_op_ext16s_i32, { "r", "rZ" } },
>  
>      { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
> +    { INDEX_op_extract_i32, { "r", "r" } },
>  
>      { INDEX_op_brcond_i32, { "rZ", "rZ" } },
>  #if use_mips32r6_instructions
> 

cc-ing Aurelien and James.

Regards,
Yongbok
Richard Henderson Oct. 27, 2016, 2:19 p.m. UTC | #2 
On 10/27/2016 06:40 AM, Yongbok Kim wrote:
>> > +    case INDEX_op_extract_i32:
>> > +        tcg_out_opc_bf(s, OPC_EXT, a0, a1, a3 + args[3] - 1, a2);
> The msbd (5th argument) must be (a2 + args[3] - 1). In fact "a3" isn't defined.
>

Yes, I eventually caught this typo when I finally got around to the 
cross-compile.  Thanks.


r~
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Patch

diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 1bcea3b..f1c3137 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -123,7 +123,7 @@  extern bool use_mips32r2_instructions;
 #define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 #define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions
 #define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
-#define TCG_TARGET_HAS_extract_i32      0
+#define TCG_TARGET_HAS_extract_i32      use_mips32r2_instructions
 #define TCG_TARGET_HAS_sextract_i32     0
 #define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 #define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index abce602..192dd49 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -1637,6 +1637,9 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_deposit_i32:
         tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
         break;
+    case INDEX_op_extract_i32:
+        tcg_out_opc_bf(s, OPC_EXT, a0, a1, a3 + args[3] - 1, a2);
+        break;
 
     case INDEX_op_brcond_i32:
         tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
@@ -1736,6 +1739,7 @@  static const TCGTargetOpDef mips_op_defs[] = {
     { INDEX_op_ext16s_i32, { "r", "rZ" } },
 
     { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+    { INDEX_op_extract_i32, { "r", "r" } },
 
     { INDEX_op_brcond_i32, { "rZ", "rZ" } },
 #if use_mips32r6_instructions