From patchwork Tue Oct 19 12:12:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxim Kuvyrkov X-Patchwork-Id: 68327 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 70A1BB6F07 for ; Tue, 19 Oct 2010 23:12:36 +1100 (EST) Received: (qmail 22447 invoked by alias); 19 Oct 2010 12:12:33 -0000 Received: (qmail 22429 invoked by uid 22791); 19 Oct 2010 12:12:28 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 19 Oct 2010 12:12:24 +0000 Received: (qmail 7219 invoked from network); 19 Oct 2010 12:12:21 -0000 Received: from unknown (HELO ?172.16.1.24?) (maxim@127.0.0.2) by mail.codesourcery.com with ESMTPA; 19 Oct 2010 12:12:21 -0000 Message-ID: <4CBD8B21.7070001@codesourcery.com> Date: Tue, 19 Oct 2010 16:12:17 +0400 From: Maxim Kuvyrkov User-Agent: Mozilla/5.0 (Macintosh; U; Intel Mac OS X 10.6; en-US; rv:1.9.2.9) Gecko/20100915 Thunderbird/3.1.4 MIME-Version: 1.0 To: "H.J. Lu" CC: gcc-patches , Richard Henderson , Bernd Schmidt , "H.J. Lu" Subject: Re: 0001-Basic-support-for-Core-i7 References: <4CBD7F43.3050209@codesourcery.com> <4CBD805D.6000208@codesourcery.com> In-Reply-To: X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 10/19/10 3:31 PM, H.J. Lu wrote: > On Tue, Oct 19, 2010 at 4:26 AM, Maxim Kuvyrkov wrote: >> This patch adds handling of "corei7" to -mtune= and -march= options. Tuning >> for -mtune=corei7 is set to that of -mtune=generic or -mtune=generic64 >> depending on the selected ABI. >> >> Tested by bootstrapping on i686-pc-linux-gnu. >> >> OK to commit? >> > > I suggest you use > > if (TARGET_64BIT) > { > } > else > switch (ix86_tune) > { > case PROCESSOR_GENERIC64: Good suggestion. Here is an updated patch. OK to commit? Thank you, diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 33510a7..71e0242 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2894,6 +2894,9 @@ ix86_option_override_internal (bool main_args_p) {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16}, + {"corei7", PROCESSOR_GENERIC64, CPU_GENERIC64, + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSSE3 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_CX16}, {"atom", PROCESSOR_ATOM, CPU_ATOM, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE}, @@ -3233,23 +3236,40 @@ ix86_option_override_internal (bool main_args_p) { ix86_schedule = processor_alias_table[i].schedule; ix86_tune = processor_alias_table[i].processor; - if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) + if (TARGET_64BIT) { - if (ix86_tune_defaulted) + if (!(processor_alias_table[i].flags & PTA_64BIT)) { - ix86_tune_string = "x86-64"; - for (i = 0; i < pta_size; i++) - if (! strcmp (ix86_tune_string, - processor_alias_table[i].name)) - break; - ix86_schedule = processor_alias_table[i].schedule; - ix86_tune = processor_alias_table[i].processor; + if (ix86_tune_defaulted) + { + ix86_tune_string = "x86-64"; + for (i = 0; i < pta_size; i++) + if (! strcmp (ix86_tune_string, + processor_alias_table[i].name)) + break; + ix86_schedule = processor_alias_table[i].schedule; + ix86_tune = processor_alias_table[i].processor; + } + else + error ("CPU you selected does not support x86-64 " + "instruction set"); + } + } + else + { + /* Adjust tuning when compiling for 32-bit ABI. */ + switch (ix86_tune) + { + case PROCESSOR_GENERIC64: + ix86_tune = PROCESSOR_GENERIC32; + ix86_schedule = CPU_PENTIUMPRO; + break; + + default: + break; } - else - error ("CPU you selected does not support x86-64 " - "instruction set"); } - /* Intel CPUs have always interpreted SSE prefetch instructions as + /* Intel CPUs have always interpreted SSE prefetch instructions as NOPs; so, we can enable SSE prefetch instructions even when -mtune (rather than -march) points us to a processor that has them. However, the VIA C3 gives a SIGILL, so we only do that for i686 and