From patchwork Tue Oct 19 09:06:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F2E25B70D1 for ; Tue, 19 Oct 2010 20:16:24 +1100 (EST) Received: from localhost ([127.0.0.1]:56946 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P88Iu-0007eX-At for incoming@patchwork.ozlabs.org; Tue, 19 Oct 2010 05:16:20 -0400 Received: from [140.186.70.92] (port=55862 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P889w-0002cO-1B for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:07:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P889i-0006NN-Mj for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:07:03 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:32864) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P889i-0006Mr-7b for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:06:50 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 2AC33873C7; Tue, 19 Oct 2010 18:06:44 +0900 (JST) Received: (nullmailer pid 27250 invoked by uid 1000); Tue, 19 Oct 2010 09:06:41 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Tue, 19 Oct 2010 18:06:28 +0900 Message-Id: <0b7a595fb1ce918fa4763657402518433d97faa4.1287478251.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v5 01/14] pci: introduce helper functions to test-and-{clear, set} mask in configuration space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch introduces helper functions to test-and-{clear, set} mask in configuration space. pci_{byte, word, long, quad}_test_and_{clear, set}_mask(). They will be used later. Signed-off-by: Isaku Yamahata --- hw/pci.h | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 70 insertions(+), 0 deletions(-) diff --git a/hw/pci.h b/hw/pci.h index d8b399f..752e652 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -323,6 +323,76 @@ pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val) pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val); } +/* + * helper functions to do bit mask operation on configuration space. + * Just to set bit, use test-and-set and discard returned value. + * Just to clear bit, use test-and-clear and discard returned value. + * NOTE: They aren't atomic. + */ +static inline uint8_t +pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) +{ + uint8_t val = pci_get_byte(config); + pci_set_byte(config, val & ~mask); + return val & mask; +} + +static inline uint8_t +pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) +{ + uint8_t val = pci_get_byte(config); + pci_set_byte(config, val | mask); + return val & mask; +} + +static inline uint16_t +pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) +{ + uint16_t val = pci_get_word(config); + pci_set_word(config, val & ~mask); + return val & mask; +} + +static inline uint16_t +pci_word_test_and_set_mask(uint8_t *config, uint16_t mask) +{ + uint16_t val = pci_get_word(config); + pci_set_word(config, val | mask); + return val & mask; +} + +static inline uint32_t +pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask) +{ + uint32_t val = pci_get_long(config); + pci_set_long(config, val & ~mask); + return val & mask; +} + +static inline uint32_t +pci_long_test_and_set_mask(uint8_t *config, uint32_t mask) +{ + uint32_t val = pci_get_long(config); + pci_set_long(config, val | mask); + return val & mask; +} + +static inline uint64_t +pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask) +{ + uint64_t val = pci_get_quad(config); + pci_set_quad(config, val & ~mask); + return val & mask; +} + +static inline uint64_t +pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask) +{ + uint64_t val = pci_get_quad(config); + pci_set_quad(config, val | mask); + return val & mask; +} + typedef int (*pci_qdev_initfn)(PCIDevice *dev); typedef struct { DeviceInfo qdev;