From patchwork Tue Oct 19 09:06:31 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8F134B6F10 for ; Tue, 19 Oct 2010 20:11:00 +1100 (EST) Received: from localhost ([127.0.0.1]:37669 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P88Dh-000467-Ip for incoming@patchwork.ozlabs.org; Tue, 19 Oct 2010 05:10:57 -0400 Received: from [140.186.70.92] (port=55789 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P889m-0002YV-1p for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:07:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P889g-0006M4-UE for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:06:53 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:32837) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P889g-0006LZ-FX for qemu-devel@nongnu.org; Tue, 19 Oct 2010 05:06:48 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 3CB1F873B0; Tue, 19 Oct 2010 18:06:42 +0900 (JST) Received: (nullmailer pid 27257 invoked by uid 1000); Tue, 19 Oct 2010 09:06:41 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Tue, 19 Oct 2010 18:06:31 +0900 Message-Id: <8370077d844866e4b4b2866f16c21a948f84c792.1287478251.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v5 04/14] pci/bridge: fix pci_bridge_reset() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The default value of base/limit registers aren't specified in the spec. So pci_bridge_reset() shouldn't touch them. Instead, introduced two functions to reset those registers in a way of typical implementation. zero base/limit registers or disable forwarding. They will be used later. Signed-off-by: Isaku Yamahata --- Changes v4 -> v5: - drop the lines in pci_bridge_reset() - introduced two functions to reset base/limit registers. --- hw/pci_bridge.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++------- hw/pci_bridge.h | 2 + 2 files changed, 51 insertions(+), 8 deletions(-) diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 638e3b3..de75e6a 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -151,6 +151,46 @@ void pci_bridge_write_config(PCIDevice *d, } } +void pci_bridge_reset_zero_base_limit(PCIDevice *dev) +{ + uint8_t *conf = dev->config; + + pci_byte_test_and_clear_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); + pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); + pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); +} + +void pci_bridge_reset_disable_base_limit(PCIDevice *dev) +{ + uint8_t *conf = dev->config; + + pci_byte_test_and_set_mask(conf + PCI_IO_BASE, + PCI_IO_RANGE_MASK & 0xff); + pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, + PCI_IO_RANGE_MASK & 0xff); + pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT, + PCI_MEMORY_RANGE_MASK & 0xffff); + pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE, + PCI_PREF_RANGE_MASK & 0xffff); + pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_MASK & 0xffff); + pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); + pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); +} + /* reset bridge specific configuration registers */ void pci_bridge_reset_reg(PCIDevice *dev) { @@ -161,14 +201,15 @@ void pci_bridge_reset_reg(PCIDevice *dev) conf[PCI_SUBORDINATE_BUS] = 0; conf[PCI_SEC_LATENCY_TIMER] = 0; - conf[PCI_IO_BASE] = 0; - conf[PCI_IO_LIMIT] = 0; - pci_set_word(conf + PCI_MEMORY_BASE, 0); - pci_set_word(conf + PCI_MEMORY_LIMIT, 0); - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0); - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0); - pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); - pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); + /* + * the default values for base/limit registers aren't specified + * in the PCI-to-PCI-bridge spec. So we don't thouch them here. + * Each implementation can override it. + * typical implementation does + * - zero registers: pci_bridge_reset_zer_base_limit() + * or + * - disable forwarding: pci_bridge_reset_disable_base_limit() + */ pci_set_word(conf + PCI_BRIDGE_CONTROL, 0); } diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h index f6fade0..2359684 100644 --- a/hw/pci_bridge.h +++ b/hw/pci_bridge.h @@ -39,6 +39,8 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len); +void pci_bridge_reset_zero_base_limit(PCIDevice *dev); +void pci_bridge_reset_disable_base_limit(PCIDevice *dev); void pci_bridge_reset_reg(PCIDevice *dev); void pci_bridge_reset(DeviceState *qdev);