Patchwork Add support for async page fault to qemu

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Submitter Gleb Natapov
Date Oct. 18, 2010, 1:25 p.m.
Message ID <20101018132538.GC10207@redhat.com>
Download mbox | patch
Permalink /patch/68182/
State New
Headers show

Comments

Gleb Natapov - Oct. 18, 2010, 1:25 p.m.
Add save/restore of MSR for migration and cpuid bit.

Signed-off-by: Gleb Natapov <gleb@redhat.com>
--
			Gleb.
Juan Quintela - Oct. 18, 2010, 3:48 p.m.
Gleb Natapov <gleb@redhat.com> wrote:
> Add save/restore of MSR for migration and cpuid bit.

It is there a way to test if async page faults are in use?
if so, we can add a subsection instead of changing the cpuversion.

I think that at some point we are going to need a bitmap that indicates
what MSR's have been used or something like that.

What do you think?

Later, Juan.
Avi Kivity - Oct. 18, 2010, 3:53 p.m.
On 10/18/2010 05:48 PM, Juan Quintela wrote:
> Gleb Natapov<gleb@redhat.com>  wrote:
> >  Add save/restore of MSR for migration and cpuid bit.
>
> It is there a way to test if async page faults are in use?

Yes, msr != 0 -> need a subsection.  Good idea.

> if so, we can add a subsection instead of changing the cpuversion.
>
> I think that at some point we are going to need a bitmap that indicates
> what MSR's have been used or something like that.
>
> What do you think?

We just need to check if an msr is different from its default value 
(which we can get by reading msrs immediately after the initial reset).

Currently the reset code assumes msr reset value is zero, that's wrong.
Gleb Natapov - Oct. 18, 2010, 4:29 p.m.
On Mon, Oct 18, 2010 at 05:48:16PM +0200, Juan Quintela wrote:
> Gleb Natapov <gleb@redhat.com> wrote:
> > Add save/restore of MSR for migration and cpuid bit.
> 
> It is there a way to test if async page faults are in use?
> if so, we can add a subsection instead of changing the cpuversion.
> 
Yeah. Good idea. Forgot about our cool new subsection feature.

--
			Gleb.

Patch

diff --git a/qemu-kvm-x86.c b/qemu-kvm-x86.c
index bb09fd8..5d8c428 100644
--- a/qemu-kvm-x86.c
+++ b/qemu-kvm-x86.c
@@ -678,6 +678,9 @@  static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
         env->mcg_ctl = entry->data;
         break;
 #endif
+    case MSR_KVM_ASYNC_PF_EN:
+        env->async_pf_en_msr = entry->data;
+        break;
     default:
 #ifdef KVM_CAP_MCE
         if (entry->index >= MSR_MC0_CTL &&
@@ -967,6 +970,7 @@  void kvm_arch_load_regs(CPUState *env, int level)
         }
         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME, env->system_time_msr);
         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
+        kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
     }
 #ifdef KVM_CAP_MCE
     if (env->mcg_cap) {
@@ -1186,6 +1190,7 @@  void kvm_arch_save_regs(CPUState *env)
 #endif
     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
     msrs[n++].index = MSR_KVM_WALL_CLOCK;
+    msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
 
 #ifdef KVM_CAP_MCE
     if (env->mcg_cap) {
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 8b6efed..154b76b 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -669,6 +669,7 @@  typedef struct CPUX86State {
 #endif
     uint64_t system_time_msr;
     uint64_t wall_clock_msr;
+    uint64_t async_pf_en_msr;
 
     uint64_t tsc;
 
@@ -923,7 +924,7 @@  CPUState *pc_new_cpu(const char *cpu_model);
 #define cpu_list_id x86_cpu_list
 #define cpudef_setup	x86_cpudef_setup
 
-#define CPU_SAVE_VERSION 12
+#define CPU_SAVE_VERSION 13
 
 /* MMU modes definitions */
 #define MMU_MODE0_SUFFIX _kernel
diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c
index d63fdcb..0ee1f88 100644
--- a/target-i386/cpuid.c
+++ b/target-i386/cpuid.c
@@ -73,7 +73,7 @@  static const char *ext3_feature_name[] = {
 };
 
 static const char *kvm_feature_name[] = {
-    "kvmclock", "kvm_nopiodelay", "kvm_mmu", NULL, NULL, NULL, NULL, NULL,
+    "kvmclock", "kvm_nopiodelay", "kvm_mmu", NULL, "kvm_asyncpf", NULL, NULL, NULL,
     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index f4fc063..0eb1e90 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -151,6 +151,9 @@  struct kvm_para_features {
 #ifdef KVM_CAP_PV_MMU
         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 #endif
+#ifdef KVM_CAP_ASYNC_PF
+        { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
+#endif
         { -1, -1 }
 };
 
@@ -672,6 +675,7 @@  static int kvm_put_msrs(CPUState *env, int level)
         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
                           env->system_time_msr);
         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
+        kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
     }
 
     msr_data.info.nmsrs = n;
@@ -880,6 +884,7 @@  static int kvm_get_msrs(CPUState *env)
 #endif
     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
     msrs[n++].index = MSR_KVM_WALL_CLOCK;
+    msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
 
     msr_data.info.nmsrs = n;
     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
@@ -926,6 +931,9 @@  static int kvm_get_msrs(CPUState *env)
         case MSR_VM_HSAVE_PA:
             env->vm_hsave = msrs[i].data;
             break;
+	case MSR_KVM_ASYNC_PF_EN:
+            env->async_pf_en_msr = msrs[i].data;
+            break;
         }
     }
 
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 4398801..092c901 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -474,6 +474,9 @@  static const VMStateDescription vmstate_cpu = {
         VMSTATE_UINT64_V(xcr0, CPUState, 12),
         VMSTATE_UINT64_V(xstate_bv, CPUState, 12),
         VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),
+
+	/* KVM async pf msr */
+        VMSTATE_UINT64_V(async_pf_en_msr, CPUState, 13),
         VMSTATE_END_OF_LIST()
         /* The above list is not sorted /wrt version numbers, watch out! */
     }