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[U-Boot,v2,1/3] drivers: net: phy: atheros: add separate config for AR8031

Message ID 20161013140338.24660-2-mugunthanvnm@ti.com
State Accepted
Commit ce412b7
Delegated to: Joe Hershberger
Headers show

Commit Message

Mugunthan V N Oct. 13, 2016, 2:03 p.m. UTC 
In the current driver implementation, config() callback is common
for AR8035 and AR8031 phy. In config() callback, driver tries to
configure MMD Access Control Register and MMD Access Address Data
Register unconditionally for both phy versions which leads to
auto negotiation failure in AM335x EVMsk second port which uses
AR8031 Giga bit RGMII phy. Fixing this by adding separate config
for AR8031 phy.

Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/phy/atheros.c | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

Comments

Joe Hershberger Oct. 13, 2016, 5:38 p.m. UTC | #1 
Hi Mugunthan,

https://patchwork.ozlabs.org/patch/681801/ was applied to u-boot-net.git.

Thanks!
-Joe
diff mbox

Patch

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index e57c412..faf5175 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -8,6 +8,15 @@ 
  */
 #include <phy.h>
 
+#define AR803x_PHY_DEBUG_ADDR_REG	0x1d
+#define AR803x_PHY_DEBUG_DATA_REG	0x1e
+
+#define AR803x_DEBUG_REG_5		0x5
+#define AR803x_RGMII_TX_CLK_DLY		0x100
+
+#define AR803x_DEBUG_REG_0		0x0
+#define AR803x_RGMII_RX_CLK_DLY		0x8000
+
 static int ar8021_config(struct phy_device *phydev)
 {
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
@@ -17,6 +26,32 @@  static int ar8021_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int ar8031_config(struct phy_device *phydev)
+{
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+			  AR803x_DEBUG_REG_5);
+		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+			  AR803x_RGMII_TX_CLK_DLY);
+	}
+
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
+		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
+			  AR803x_DEBUG_REG_0);
+		phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG,
+			  AR803x_RGMII_RX_CLK_DLY);
+	}
+
+	phydev->supported = phydev->drv->features;
+
+	genphy_config_aneg(phydev);
+	genphy_restart_aneg(phydev);
+
+	return 0;
+}
+
 static int ar8035_config(struct phy_device *phydev)
 {
 	int regval;
@@ -54,7 +89,7 @@  static struct phy_driver AR8031_driver =  {
 	.uid = 0x4dd074,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
-	.config = ar8035_config,
+	.config = ar8031_config,
 	.startup = genphy_startup,
 	.shutdown = genphy_shutdown,
 };