Patchwork ibm_newemac: Add support for Arches CPU0 SGMII0 to CPU1 SGMII0

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Submitter Victor Gallardo
Date Nov. 1, 2008, 9:03 p.m.
Message ID <1225573402-28113-1-git-send-email-vgallardo@amcc.com>
Download mbox | patch
Permalink /patch/6814/
State Not Applicable
Delegated to: Josh Boyer
Headers show

Comments

Victor Gallardo - Nov. 1, 2008, 9:03 p.m.
On Arches, SGMII0 Rx/Tx on CPU0 is wired to SGMII0 Tx/Rx on CPU1.
Add GPCS as a phy type to allow for this.

Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
---
 arch/powerpc/boot/dts/arches.dts |    3 ++-
 drivers/net/ibm_newemac/core.c   |    5 ++++-
 drivers/net/ibm_newemac/phy.c    |   29 +++++++++++++++++++++++++++++
 3 files changed, 35 insertions(+), 2 deletions(-)
Victor Gallardo - Nov. 4, 2008, 6:29 p.m.
Hello Josh,

Have you had a chance to look at this patch.

> On Arches, SGMII0 Rx/Tx on CPU0 is wired to SGMII0 Tx/Rx on CPU1.
> Add GPCS as a phy type to allow for this.

Regards,

Victor Gallardo
Victor Gallardo - Nov. 5, 2008, 3:14 p.m.
Hello,
 
How can I figure out the and/or what is the maximum memory linux support for powerpc 4xx?

Regards,

Victor Gallardo
Deepak Pandian - Nov. 5, 2008, 4:29 p.m.
Hi Victor,

I dont really get what do you mean as memory. If it is RAM refer to your
processors datasheet.

Linux always works with virtual address which are 32 bits in length- so by
default supports 4 GB of working memory/IO space. But with the advent of
high memory this limitation has been overcome.

I am sorry if i the answer is vague - thats because your question is also
abrupt to me.

On Wed, Nov 5, 2008 at 8:44 PM, Victor Gallardo <vgallardo@amcc.com> wrote:

>  Hello,
>
> How can I figure out the and/or what is the maximum memory linux support
> for powerpc 4xx?
>
> Regards,
>
> Victor Gallardo
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
Kumar Gala - Nov. 5, 2008, 4:34 p.m.
On Nov 5, 2008, at 9:14 AM, Victor Gallardo wrote:

> Hello,
>
> How can I figure out the and/or what is the maximum memory linux  
> support for powerpc 4xx?

I'd expect the amount of memory supported to be a bit under 4G at this  
point.  There is generic work that has been going on to allow ALL  
ppc32's that have HW support for 36-bit physical to support >4G of  
memory.. however that code is likely in 2.6.29.

- k
Victor Gallardo - Nov. 5, 2008, 6:39 p.m.
> > Hello,
> >
> > How can I figure out the and/or what is the maximum memory linux 
> > support for powerpc 4xx?
> 
> I'd expect the amount of memory supported to be a bit under 4G at
> this point.  There is generic work that has been going on to allow
> ALL ppc32's that have HW support for 36-bit physical to support >4G
> of memory.. however that code is likely in 2.6.29.

Thanks, Kumar.

-Victor Gallardo

- k
Josh Boyer - Nov. 5, 2008, 9:15 p.m.
On Wed, 5 Nov 2008 10:34:32 -0600
Kumar Gala <galak@kernel.crashing.org> wrote:

> 
> On Nov 5, 2008, at 9:14 AM, Victor Gallardo wrote:
> 
> > Hello,
> >
> > How can I figure out the and/or what is the maximum memory linux  
> > support for powerpc 4xx?
> 
> I'd expect the amount of memory supported to be a bit under 4G at this  
> point.  There is generic work that has been going on to allow ALL  
> ppc32's that have HW support for 36-bit physical to support >4G of  
> memory.. however that code is likely in 2.6.29.

In 4xx-specific terms, it depends on the memory controller as well.
The older SoCs only supported 2GiB in hardware I think.  The Denali
memory controller can do 16GiB in hardware from my recollection.

But you probably already knew that.

josh
Victor Gallardo - Nov. 10, 2008, 6:07 p.m.
Hello Josh and Ben,

Who should I ask to get this patch integrated into the Linux tree?
	http://ozlabs.org/pipermail/linuxppc-dev/2008-November/064834.html

Thanks,

Victor Gallardo
Benjamin Herrenschmidt - Nov. 10, 2008, 9:40 p.m.
On Mon, 2008-11-10 at 10:07 -0800, Victor Gallardo wrote:
> Hello Josh and Ben,
> 
> Who should I ask to get this patch integrated into the Linux tree?
> 	http://ozlabs.org/pipermail/linuxppc-dev/2008-November/064834.html

Either, I've been off for a couple of weeks (new baby) which is why I
didn't get a chance to review it yet, still going through backlog.

Cheers,
Ben.
Victor Gallardo - Jan. 17, 2009, 12:14 a.m.
Hi Josh,

I see you are delegated for this patch submission any ideas when it will be accepted.

http://patchwork.ozlabs.org/patch/6814/

Thanks,

-Victor Gallardo

-----Original Message-----
From: linuxppc-dev-bounces+vgallardo=amcc.com@ozlabs.org [mailto:linuxppc-dev-bounces+vgallardo=amcc.com@ozlabs.org] On Behalf Of Victor Gallardo
Sent: Monday, November 10, 2008 10:07 AM
To: Josh Boyer; benh@kernel.crashing.org
Cc: linuxppc-dev@ozlabs.org
Subject: RE: [PATCH] ibm_newemac: Add support for Arches CPU0 SGMII0 to CPU1SGMII0

Hello Josh and Ben,

Who should I ask to get this patch integrated into the Linux tree?
	http://ozlabs.org/pipermail/linuxppc-dev/2008-November/064834.html

Thanks,

Victor Gallardo
Benjamin Herrenschmidt - Jan. 17, 2009, 3:16 a.m.
On Fri, 2009-01-16 at 16:14 -0800, Victor Gallardo wrote:
> Hi Josh,
> 
> I see you are delegated for this patch submission any ideas when it will be accepted.
> 
> http://patchwork.ozlabs.org/patch/6814/

Looks like it fell through the cracks.

Can you resend it to both our list and netdev@vger.kernel.org ? Keep
CC'me, I'll ack it and then it will be up to the networking folks to
pick it up.

Cheers,
Ben.
Benjamin Herrenschmidt - Jan. 28, 2009, 3:42 a.m.
On Fri, 2009-01-16 at 16:14 -0800, Victor Gallardo wrote:
> Hi Josh,
> 
> I see you are delegated for this patch submission any ideas when it will be accepted.
> 
> http://patchwork.ozlabs.org/patch/6814/

Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

Victor, re-send to netdev with my Ack included.

Cheers,
Ben.

> Thanks,
> 
> -Victor Gallardo
> 
> -----Original Message-----
> From: linuxppc-dev-bounces+vgallardo=amcc.com@ozlabs.org [mailto:linuxppc-dev-bounces+vgallardo=amcc.com@ozlabs.org] On Behalf Of Victor Gallardo
> Sent: Monday, November 10, 2008 10:07 AM
> To: Josh Boyer; benh@kernel.crashing.org
> Cc: linuxppc-dev@ozlabs.org
> Subject: RE: [PATCH] ibm_newemac: Add support for Arches CPU0 SGMII0 to CPU1SGMII0
> 
> Hello Josh and Ben,
> 
> Who should I ask to get this patch integrated into the Linux tree?
> 	http://ozlabs.org/pipermail/linuxppc-dev/2008-November/064834.html
> 
> Thanks,
> 
> Victor Gallardo
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

Patch

diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index d9113b1..a5f1597 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -225,7 +225,8 @@ 
 				rx-fifo-size = <4096>;
 				tx-fifo-size = <2048>;
 				phy-mode = "sgmii";
-				phy-map = <0xffffffff>;
+				phy-map = <0x00000400>;
+				phy-address = <0x0000000a>;
 				gpcs-address = <0x0000000a>;
 				tah-device = <&TAH0>;
 				tah-channel = <0>;
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 2ee2622..9b62741 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -2814,7 +2814,10 @@  static int __devinit emac_probe(struct of_device *ofdev,
 		goto err_detach_rgmii;
 
 	/* Set some link defaults before we can find out real parameters */
-	dev->phy.speed = SPEED_100;
+	if (emac_phy_gpcs(dev->phy_mode))
+		dev->phy.speed = SPEED_1000;
+	else
+		dev->phy.speed = SPEED_100;
 	dev->phy.duplex = DUPLEX_FULL;
 	dev->phy.autoneg = AUTONEG_DISABLE;
 	dev->phy.pause = dev->phy.asym_pause = 0;
diff --git a/drivers/net/ibm_newemac/phy.c b/drivers/net/ibm_newemac/phy.c
index c40cd8d..84e6e45 100644
--- a/drivers/net/ibm_newemac/phy.c
+++ b/drivers/net/ibm_newemac/phy.c
@@ -400,6 +400,18 @@  static int m88e1112_init(struct mii_phy *phy)
 	return  0;
 }
 
+static int gpcs_init(struct mii_phy *phy)
+{
+	if (phy->mode == PHY_MODE_SGMII) {
+		/* Configure GPCS interface to recommended setting for SGMII */
+		phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
+		phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
+		phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX     */
+	}
+
+	return 0;
+}
+
 static int et1011c_init(struct mii_phy *phy)
 {
 	u16 reg_short;
@@ -467,12 +479,29 @@  static struct mii_phy_def m88e1112_phy_def = {
 	.ops		= &m88e1112_phy_ops,
 };
 
+static struct mii_phy_ops gpcs_phy_ops = {
+	.init		= gpcs_init,
+	.setup_aneg	= genmii_setup_aneg,
+	.setup_forced	= genmii_setup_forced,
+	.poll_link	= genmii_poll_link,
+	.read_link	= genmii_read_link
+};
+
+static struct mii_phy_def gpcs_phy_def = {
+	.phy_id		= 0xf6d5eeef,
+	.phy_id_mask	= 0xffffffff,
+	.features	= SUPPORTED_1000baseT_Full,
+	.name		= "Internal GPCS",
+	.ops		= &gpcs_phy_ops,
+};
+
 static struct mii_phy_def *mii_phy_table[] = {
 	&et1011c_phy_def,
 	&cis8201_phy_def,
 	&bcm5248_phy_def,
 	&m88e1111_phy_def,
 	&m88e1112_phy_def,
+	&gpcs_phy_def,
 	&genmii_phy_def,
 	NULL
 };