| Message ID | 1476274533-17995-1-git-send-email-pratiyush.srivastava@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
On 10/12/2016 05:15 AM, Pratiyush Srivastava wrote: > Clear the content to zero and the ECC error bit of OCRAM1/2. > > The OCRAM must be initialized to ZERO by the unit of 8-Byte before > accessing it, or else it will generate ECC error. And the IBR has > accessed the OCRAM before this initialization, so the ECC error > status bit should to be cleared. Does the ECC error trigger any exception? Why didn't we see the error before? > > Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > --- > arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > index 19c771d..24fed46 100644 > --- a/arch/arm/cpu/armv8/start.S > +++ b/arch/arm/cpu/armv8/start.S > @@ -11,6 +11,9 @@ > #include <asm/macro.h> > #include <asm/armv8/mmu.h> > > +#define DCSR_SYS_DCFG_SBEESR2 0x20140534 > +#define DCSR_SYS_DCFG_MBEESR2 0x20140544 > + > /************************************************************************* > * > * Startup Code (reset vector) > @@ -259,10 +262,46 @@ WEAK(lowlevel_init) > #endif /* CONFIG_ARMV8_MULTIENTRY */ > > 2: > +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) > + bl fsl_ocram_init > +#endif Why do you change this weak function, not the one in lowerlevel.S? York
Hi Mingkai, > -----Original Message----- > From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] > Sent: Wednesday, October 12, 2016 5:46 PM > To: u-boot@lists.denx.de > Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava > <pratiyush.srivastava@nxp.com>; Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization > > Clear the content to zero and the ECC error bit of OCRAM1/2. > > The OCRAM must be initialized to ZERO by the unit of 8-Byte before > accessing it, or else it will generate ECC error. And the IBR has > accessed the OCRAM before this initialization, so the ECC error > status bit should to be cleared. > > Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > --- This requirement is for both ls1043 and ls1088a. was this patch taken care during ls1043a upstreaming If not, how it is being taken care for ls1043a. Same approach can be used for ls1088a --prabhakar
On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: > Hi Mingkai, > >> -----Original Message----- >> From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] >> Sent: Wednesday, October 12, 2016 5:46 PM >> To: u-boot@lists.denx.de >> Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha >> <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava >> <pratiyush.srivastava@nxp.com>; Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization >> >> Clear the content to zero and the ECC error bit of OCRAM1/2. >> >> The OCRAM must be initialized to ZERO by the unit of 8-Byte before >> accessing it, or else it will generate ECC error. And the IBR has >> accessed the OCRAM before this initialization, so the ECC error >> status bit should to be cleared. >> >> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> >> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> >> --- > > This requirement is for both ls1043 and ls1088a. was this patch taken care during ls1043a upstreaming > If not, how it is being taken care for ls1043a. Same approach can be used for ls1088a > I wonder why we don't see ECC errors before this patch. We have LS1043A boots on NAND, SD. York
Hi York, > -----Original Message----- > From: york sun > Sent: Saturday, October 22, 2016 1:39 AM > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava > <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; Mingkai Hu > <mingkai.hu@nxp.com> > Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > > On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: > > Hi Mingkai, > > > >> -----Original Message----- > >> From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] > >> Sent: Wednesday, October 12, 2016 5:46 PM > >> To: u-boot@lists.denx.de > >> Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha > >> <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava > >> <pratiyush.srivastava@nxp.com>; Hou Zhiqiang > <Zhiqiang.Hou@freescale.com> > >> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >> > >> Clear the content to zero and the ECC error bit of OCRAM1/2. > >> > >> The OCRAM must be initialized to ZERO by the unit of 8-Byte before > >> accessing it, or else it will generate ECC error. And the IBR has > >> accessed the OCRAM before this initialization, so the ECC error > >> status bit should to be cleared. > >> > >> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> > >> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > >> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > >> --- > > > > This requirement is for both ls1043 and ls1088a. was this patch taken care > during ls1043a upstreaming > > If not, how it is being taken care for ls1043a. Same approach can be used for > ls1088a > > > > I wonder why we don't see ECC errors before this patch. We have LS1043A > boots on NAND, SD. > OCRAM has a requirement of initializing before first time "read". If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). I can only guess the reason of not seeing this error as OCRAM never read before any write. Even in case of Stack, data is first written and then read. --prabhakar
On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote: > Hi York, > > >> -----Original Message----- >> From: york sun >> Sent: Saturday, October 22, 2016 1:39 AM >> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava >> <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; Mingkai Hu >> <mingkai.hu@nxp.com> >> Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization >> >> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: >>> Hi Mingkai, >>> >>>> -----Original Message----- >>>> From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] >>>> Sent: Wednesday, October 12, 2016 5:46 PM >>>> To: u-boot@lists.denx.de >>>> Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha >>>> <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava >>>> <pratiyush.srivastava@nxp.com>; Hou Zhiqiang >> <Zhiqiang.Hou@freescale.com> >>>> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization >>>> >>>> Clear the content to zero and the ECC error bit of OCRAM1/2. >>>> >>>> The OCRAM must be initialized to ZERO by the unit of 8-Byte before >>>> accessing it, or else it will generate ECC error. And the IBR has >>>> accessed the OCRAM before this initialization, so the ECC error >>>> status bit should to be cleared. >>>> >>>> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> >>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >>>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> >>>> --- >>> >>> This requirement is for both ls1043 and ls1088a. was this patch taken care >> during ls1043a upstreaming >>> If not, how it is being taken care for ls1043a. Same approach can be used for >> ls1088a >>> >> >> I wonder why we don't see ECC errors before this patch. We have LS1043A >> boots on NAND, SD. >> > > OCRAM has a requirement of initializing before first time "read". > If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). > > I can only guess the reason of not seeing this error as OCRAM never read before any write. > Even in case of Stack, data is first written and then read. > Is there a case you want to read from OCRAM before writing anything to it? Why don't we need to do so for SPL or LSCH3? York
> -----Original Message----- > From: york sun > Sent: Tuesday, October 25, 2016 12:15 AM > To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush > Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; Mingkai > Hu <mingkai.hu@nxp.com> > Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > > On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote: > > Hi York, > > > > > >> -----Original Message----- > >> From: york sun > >> Sent: Saturday, October 22, 2016 1:39 AM > >> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush > >> Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; > >> Mingkai Hu <mingkai.hu@nxp.com> > >> Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > >> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >> > >> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: > >>> Hi Mingkai, > >>> > >>>> -----Original Message----- > >>>> From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] > >>>> Sent: Wednesday, October 12, 2016 5:46 PM > >>>> To: u-boot@lists.denx.de > >>>> Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha > >>>> <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava > >>>> <pratiyush.srivastava@nxp.com>; Hou Zhiqiang > >> <Zhiqiang.Hou@freescale.com> > >>>> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >>>> > >>>> Clear the content to zero and the ECC error bit of OCRAM1/2. > >>>> > >>>> The OCRAM must be initialized to ZERO by the unit of 8-Byte before > >>>> accessing it, or else it will generate ECC error. And the IBR has > >>>> accessed the OCRAM before this initialization, so the ECC error > >>>> status bit should to be cleared. > >>>> > >>>> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> > >>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> > >>>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > >>>> --- > >>> > >>> This requirement is for both ls1043 and ls1088a. was this patch > >>> taken care > >> during ls1043a upstreaming > >>> If not, how it is being taken care for ls1043a. Same approach can > >>> be used for > >> ls1088a > >>> > >> > >> I wonder why we don't see ECC errors before this patch. We have > >> LS1043A boots on NAND, SD. > >> > > > > OCRAM has a requirement of initializing before first time "read". > > If user reads OCRAM before **initializing**; ECC error will come. (u-boot is > not handling this error for now). > > > > I can only guess the reason of not seeing this error as OCRAM never read > before any write. > > Even in case of Stack, data is first written and then read. > > > > Is there a case you want to read from OCRAM before writing anything to it? > Why don't we need to do so for SPL or LSCH3? > Hi York, For secure boot case, the bootrom uses the OCRAM as workspace but does not Cleare the after the using, which will trigger this issue. Thanks, Mingkai
Hi York, >-----Original Message----- >From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of york sun >Sent: Monday, October 24, 2016 9:45 PM >To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava <pratiyush.srivastava@nxp.com>; u- >boot@lists.denx.de; Mingkai Hu <mingkai.hu@nxp.com> >Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >Subject: Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization > >On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote: >> Hi York, >> >> >>> -----Original Message----- >>> From: york sun >>> Sent: Saturday, October 22, 2016 1:39 AM >>> To: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush >>> Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; >>> Mingkai Hu <mingkai.hu@nxp.com> >>> Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >>> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization >>> >>> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: >>>> Hi Mingkai, >>>> >>>>> -----Original Message----- >>>>> From: Pratiyush Srivastava [mailto:pratiyush.srivastava@nxp.com] >>>>> Sent: Wednesday, October 12, 2016 5:46 PM >>>>> To: u-boot@lists.denx.de >>>>> Cc: york sun <york.sun@nxp.com>; Prabhakar Kushwaha >>>>> <prabhakar.kushwaha@nxp.com>; Pratiyush Srivastava >>>>> <pratiyush.srivastava@nxp.com>; Hou Zhiqiang >>> <Zhiqiang.Hou@freescale.com> >>>>> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization >>>>> >>>>> Clear the content to zero and the ECC error bit of OCRAM1/2. >>>>> >>>>> The OCRAM must be initialized to ZERO by the unit of 8-Byte before >>>>> accessing it, or else it will generate ECC error. And the IBR has >>>>> accessed the OCRAM before this initialization, so the ECC error >>>>> status bit should to be cleared. >>>>> >>>>> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com> >>>>> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >>>>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> >>>>> --- >>>> >>>> This requirement is for both ls1043 and ls1088a. was this patch >>>> taken care >>> during ls1043a upstreaming >>>> If not, how it is being taken care for ls1043a. Same approach can >>>> be used for >>> ls1088a >>>> >>> >>> I wonder why we don't see ECC errors before this patch. We have >>> LS1043A boots on NAND, SD. >>> >> >> OCRAM has a requirement of initializing before first time "read". >> If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). >> >> I can only guess the reason of not seeing this error as OCRAM never read before any write. >> Even in case of Stack, data is first written and then read. >> > >Is there a case you want to read from OCRAM before writing anything to it? Why don't we need to do so for SPL or LSCH3? This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also. Regards Calvin
On 10/24/2016 09:30 PM, Calvin Johnson wrote: >>>> I wonder why we don't see ECC errors before this patch. We have >>>> LS1043A boots on NAND, SD. >>>> >>> >>> OCRAM has a requirement of initializing before first time "read". >>> If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). >>> >>> I can only guess the reason of not seeing this error as OCRAM never read before any write. >>> Even in case of Stack, data is first written and then read. >>> >> >> Is there a case you want to read from OCRAM before writing anything to it? Why don't we need to do so for SPL or LSCH3? > > This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also. > How about LSCH3? We have LS2080A secure boot. York
Hi York, >-----Original Message----- >From: york sun >Sent: Wednesday, October 26, 2016 10:09 PM >To: Calvin Johnson <calvin.johnson@nxp.com>; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush >Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; Mingkai Hu <mingkai.hu@nxp.com> >Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >On 10/24/2016 09:30 PM, Calvin Johnson wrote: > >>>>> I wonder why we don't see ECC errors before this patch. We have >>>>> LS1043A boots on NAND, SD. >>>>> >>>> >>>> OCRAM has a requirement of initializing before first time "read". >>>> If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). >>>> >>>> I can only guess the reason of not seeing this error as OCRAM never read before any write. >>>> Even in case of Stack, data is first written and then read. >>>> >>> >>> Is there a case you want to read from OCRAM before writing anything to it? Why don't we need to do so for SPL or >LSCH3? >> >> This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also. >> > >How about LSCH3? We have LS2080A secure boot. I don't know about LS2080A. Prabhakar or Ruchika(copied) may be able to comment on this. Regards Calvin
On 10/27/2016 02:47 AM, Calvin Johnson wrote: > Hi York, > >> -----Original Message----- >> From: york sun >> Sent: Wednesday, October 26, 2016 10:09 PM >> To: Calvin Johnson <calvin.johnson@nxp.com>; Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Pratiyush >> Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; Mingkai Hu <mingkai.hu@nxp.com> >> Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization >> >> On 10/24/2016 09:30 PM, Calvin Johnson wrote: >> >>>>>> I wonder why we don't see ECC errors before this patch. We have >>>>>> LS1043A boots on NAND, SD. >>>>>> >>>>> >>>>> OCRAM has a requirement of initializing before first time "read". >>>>> If user reads OCRAM before **initializing**; ECC error will come. (u-boot is not handling this error for now). >>>>> >>>>> I can only guess the reason of not seeing this error as OCRAM never read before any write. >>>>> Even in case of Stack, data is first written and then read. >>>>> >>>> >>>> Is there a case you want to read from OCRAM before writing anything to it? Why don't we need to do so for SPL or >> LSCH3? >>> >>> This issue will be seen ONLY in secure boot. It was reproduced on LS1043A also. >>> >> >> How about LSCH3? We have LS2080A secure boot. > > I don't know about LS2080A. Prabhakar or Ruchika(copied) may be able to comment on this. > Please follow up on this thread. We need to understand when and where OCRAM needs to be cleared. York
On 11/07/2016 10:36 AM, york.sun@nxp.com wrote: > On 10/27/2016 02:47 AM, Calvin Johnson wrote: >> Hi York, >> >>> -----Original Message----- >>> From: york sun >>> Sent: Wednesday, October 26, 2016 10:09 PM >>> To: Calvin Johnson <calvin.johnson@nxp.com>; Prabhakar Kushwaha >>> <prabhakar.kushwaha@nxp.com>; Pratiyush >>> Srivastava <pratiyush.srivastava@nxp.com>; u-boot@lists.denx.de; >>> Mingkai Hu <mingkai.hu@nxp.com> >>> Cc: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> >>> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization >>> >>> On 10/24/2016 09:30 PM, Calvin Johnson wrote: >>> >>>>>>> I wonder why we don't see ECC errors before this patch. We have >>>>>>> LS1043A boots on NAND, SD. >>>>>>> >>>>>> >>>>>> OCRAM has a requirement of initializing before first time "read". >>>>>> If user reads OCRAM before **initializing**; ECC error will come. >>>>>> (u-boot is not handling this error for now). >>>>>> >>>>>> I can only guess the reason of not seeing this error as OCRAM >>>>>> never read before any write. >>>>>> Even in case of Stack, data is first written and then read. >>>>>> >>>>> >>>>> Is there a case you want to read from OCRAM before writing anything >>>>> to it? Why don't we need to do so for SPL or >>> LSCH3? >>>> >>>> This issue will be seen ONLY in secure boot. It was reproduced on >>>> LS1043A also. >>>> >>> >>> How about LSCH3? We have LS2080A secure boot. >> >> I don't know about LS2080A. Prabhakar or Ruchika(copied) may be able >> to comment on this. >> > > Please follow up on this thread. We need to understand when and where > OCRAM needs to be cleared. > Can Prabhakar or Ruchika verify this OCRAM init on LSCH3? If it is required and effective, we can take this patch. York
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 19c771d..24fed46 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -11,6 +11,9 @@ #include <asm/macro.h> #include <asm/armv8/mmu.h> +#define DCSR_SYS_DCFG_SBEESR2 0x20140534 +#define DCSR_SYS_DCFG_MBEESR2 0x20140544 + /************************************************************************* * * Startup Code (reset vector) @@ -259,10 +262,46 @@ WEAK(lowlevel_init) #endif /* CONFIG_ARMV8_MULTIENTRY */ 2: +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) + bl fsl_ocram_init +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD) +ENTRY(fsl_ocram_init) + mov x28, lr /* Save LR */ + bl fsl_clear_ocram + bl fsl_ocram_clear_ecc_err + mov lr, x28 /* Restore LR */ + ret +ENDPROC(fsl_ocram_init) + +ENTRY(fsl_clear_ocram) +/* Clear OCRAM */ + ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE + ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE) + mov x2, #0 +clear_loop: + str x2, [x0] + add x0, x0, #8 + cmp x0, x1 + b.lo clear_loop + ret +ENDPROC(fsl_clear_ocram) + +ENTRY(fsl_ocram_clear_ecc_err) + /* OCRAM1/2 ECC status bit */ + mov w1, #0x60 + ldr x0, =DCSR_SYS_DCFG_SBEESR2 + str w1, [x0] + ldr x0, =DCSR_SYS_DCFG_MBEESR2 + str w1, [x0] + ret +ENDPROC(fsl_ocram_init) +#endif + WEAK(smp_kick_all_cpus) /* Kick secondary cpus up by SGI 0 interrupt */ #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)