From patchwork Mon Oct 18 03:17:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68110 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 139B8B70F3 for ; Mon, 18 Oct 2010 14:43:10 +1100 (EST) Received: from localhost ([127.0.0.1]:46178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7gcs-0005KI-U5 for incoming@patchwork.ozlabs.org; Sun, 17 Oct 2010 23:43:06 -0400 Received: from [140.186.70.92] (port=51852 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7gEi-0002Z8-BE for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P7gEe-00044h-AU for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:08 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:50715) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P7gEd-00043Z-J4 for qemu-devel@nongnu.org; Sun, 17 Oct 2010 23:18:04 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id CFE0A188E7; Mon, 18 Oct 2010 12:17:58 +0900 (JST) Received: (nullmailer pid 16522 invoked by uid 1000); Mon, 18 Oct 2010 03:17:56 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Mon, 18 Oct 2010 12:17:52 +0900 Message-Id: X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v4 11/15] ioh3420: pcie root port in X58 ioh X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implements pcie root port switch in intel X58 ioh whose device id is 0x3420. Signed-off-by: Isaku Yamahata --- Changes v3 -> v4: - rename pcie_root -> ioh3420 - compilation adjustment. Changes v2 -> v3: - compilation adjustment. --- Makefile.objs | 1 + hw/ioh3420.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/ioh3420.h | 10 +++ 3 files changed, 239 insertions(+), 0 deletions(-) create mode 100644 hw/ioh3420.c create mode 100644 hw/ioh3420.h diff --git a/Makefile.objs b/Makefile.objs index 6c3b84a..cf7d2e9 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -140,6 +140,7 @@ hw-obj-y = hw-obj-y += vl.o loader.o hw-obj-y += virtio.o virtio-console.o hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o pci_bridge.o +hw-obj-y += ioh3420.o hw-obj-y += watchdog.o hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o hw-obj-$(CONFIG_ECC) += ecc.o diff --git a/hw/ioh3420.c b/hw/ioh3420.c new file mode 100644 index 0000000..19330c3 --- /dev/null +++ b/hw/ioh3420.c @@ -0,0 +1,228 @@ +/* + * ioh3420.c + * Intel X58 north bridge IOH + * PCI Express root port device id 3420 + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "pci_ids.h" +#include "msi.h" +#include "pcie.h" +#include "ioh3420.h" + +#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ +#define PCI_DEVICE_ID_IOH_REV 0x2 +#define IOH_EP_SSVID_OFFSET 0x40 +#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL +#define IOH_EP_SSVID_SSID 0 +#define IOH_EP_MSI_OFFSET 0x60 +#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT +#define IOH_EP_MSI_NR_VECTOR 2 +#define IOH_EP_EXP_OFFSET 0x90 +#define IOH_EP_AER_OFFSET 0x100 + +/* + * If two MSI vector are allocated, Advanced Error Interrupt Message Number + * is 1. otherwise 0. + * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. + */ +static uint8_t ioh3420_aer_vector(const PCIDevice *d) +{ + switch (msi_nr_vectors_allocated(d)) { + case 1: + return 0; + case 2: + return 1; + case 4: + case 8: + case 16: + case 32: + default: + break; + } + abort(); + return 0; +} + +static void ioh3420_aer_vector_update(PCIDevice *d) +{ + pcie_aer_root_set_vector(d, ioh3420_aer_vector(d)); +} + +static void ioh3420_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + uint16_t sltctl = + pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL); + uint32_t uncorsta = + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_UNCOR_STATUS); + uint32_t root_cmd = + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); + + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + ioh3420_aer_vector_update(d); + pcie_cap_slot_write_config(d, address, val, len, sltctl); + pcie_aer_write_config(d, address, val, len, uncorsta); + pcie_aer_root_write_config(d, address, val, len, root_cmd); + pci_clear_written_write_config(d, address, val, len); +} + +static void ioh3420_reset(DeviceState *qdev) +{ + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); + msi_reset(d); + ioh3420_aer_vector_update(d); + pcie_cap_root_reset(d); + pcie_cap_deverr_reset(d); + pcie_cap_slot_reset(d); + pcie_aer_root_reset(d); + pci_bridge_reset(qdev); +} + +static int ioh3420_initfn(PCIDevice *d) +{ + PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); + PCIEPort *p = DO_UPCAST(PCIEPort, br, br); + PCIESlot *s = DO_UPCAST(PCIESlot, port, p); + int rc; + + rc = pci_bridge_initfn(d); + if (rc < 0) { + return rc; + } + + d->config[PCI_REVISION_ID] = PCI_DEVICE_ID_IOH_REV; + pcie_port_init_reg(d); + + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); + pci_config_set_device_id(d->config, PCI_DEVICE_ID_IOH_EPORT); + + rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET, + IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID); + if (rc < 0) { + return rc; + } + rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, + IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, + IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); + if (rc < 0) { + return rc; + } + rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); + if (rc < 0) { + return rc; + } + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s->slot); + pcie_chassis_create(s->chassis); + rc = pcie_chassis_add_slot(s); + if (rc < 0) { + return rc; + } + pcie_cap_root_init(d); + pcie_aer_init(d, IOH_EP_AER_OFFSET); + pcie_aer_root_init(d); + ioh3420_aer_vector_update(d); + return 0; +} + +static int ioh3420_exitfn(PCIDevice *d) +{ + pcie_aer_exit(d); + msi_uninit(d); + pcie_cap_exit(d); + return pci_bridge_exitfn(d); +} + +PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot) +{ + PCIDevice *d; + PCIBridge *br; + DeviceState *qdev; + + d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420"); + if (!d) { + return NULL; + } + br = DO_UPCAST(PCIBridge, dev, d); + + qdev = &br->dev.qdev; + pci_bridge_map_irq(br, bus_name, map_irq); + qdev_prop_set_uint8(qdev, "port", port); + qdev_prop_set_uint8(qdev, "chassis", chassis); + qdev_prop_set_uint16(qdev, "slot", slot); + qdev_init_nofail(qdev); + + return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); +} + +static const VMStateDescription vmstate_ioh3420 = { + .name = "ioh-3240-express-root-port", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), + VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, + vmstate_pcie_aer_log, PCIEAERLog), + VMSTATE_END_OF_LIST() + } +}; + +static PCIDeviceInfo ioh3420_info = { + .qdev.name = "ioh3420", + .qdev.desc = "Intel IOH device id 3420 PCIE Root Port", + .qdev.size = sizeof(PCIESlot), + .qdev.reset = ioh3420_reset, + .qdev.vmsd = &vmstate_ioh3420, + + .is_express = 1, + .is_bridge = 1, + .config_write = ioh3420_write_config, + .init = ioh3420_initfn, + .exit = ioh3420_exitfn, + + .qdev.props = (Property[]) { + DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), + DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), + DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void ioh3420_register(void) +{ + pci_qdev_register(&ioh3420_info); +} + +device_init(ioh3420_register); + +/* + * Local variables: + * c-indent-level: 4 + * c-basic-offset: 4 + * tab-width: 8 + * indent-tab-mode: nil + * End: + */ diff --git a/hw/ioh3420.h b/hw/ioh3420.h new file mode 100644 index 0000000..68c523a --- /dev/null +++ b/hw/ioh3420.h @@ -0,0 +1,10 @@ +#ifndef QEMU_IOH3420_H +#define QEMU_IOH3420_H + +#include "pcie_port.h" + +PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot); + +#endif /* QEMU_IOH3420_H */