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[14/29] target-sparc: use direct address translation in hyperprivileged mode

Message ID 357f661c-312c-e7b2-adc3-20d1b1fda10c@twiddle.net
State New
Headers show

Commit Message

Richard Henderson Oct. 11, 2016, 5:55 a.m. UTC 
On 10/01/2016 05:05 AM, Artyom Tarasenko wrote:
> Implement translation behavior described in the chapter 13.7 of
> "UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005".
>
> Please note that QEMU doesn't impelement Real->Physical address
> translation. The "Real Address" is always the "Physical Address".
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
>  target-sparc/mmu_helper.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index 32b629f..bef63f8 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -498,7 +498,8 @@ static int get_physical_address_data(CPUSPARCState *env,
>      int is_user = (mmu_idx == MMU_USER_IDX ||
>                     mmu_idx == MMU_USER_SECONDARY_IDX);
>
> -    if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
> +    if ((env->lsu & DMMU_E) == 0 || cpu_hypervisor_mode(env)) {
> +        /* direct translation VA -> PA */
>          *physical = ultrasparc_truncate_physical(address);
>          *prot = PAGE_READ | PAGE_WRITE;
>          return 0;
> @@ -617,8 +618,9 @@ static int get_physical_address_code(CPUSPARCState *env,
>      int is_user = (mmu_idx == MMU_USER_IDX ||
>                     mmu_idx == MMU_USER_SECONDARY_IDX);
>
> -    if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
> -        /* IMMU disabled */
> +    if (((env->lsu & IMMU_E) == 0) || (env->pstate & PS_RED) != 0
> +        || cpu_hypervisor_mode(env)) {
> +        /* direct translation VA -> PA */

If we let this depend on my MMU_PHYS_IDX patch, this becomes
diff mbox

Patch

>From b1cb710579877de99fdbc03f30f43622057bb4ca Mon Sep 17 00:00:00 2001
From: Artyom Tarasenko <atar4qemu@gmail.com>
Date: Sat, 1 Oct 2016 12:05:18 +0200
Subject: [PATCH 14/31] target-sparc: use direct address translation in
 hyperprivileged mode
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Implement translation behavior described in the chapter 13.7 of
"UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005".

Please note that QEMU doesn't impelement Real->Physical address
translation. The "Real Address" is always the "Physical Address".

[rth: Therefore we can merge MMU_HYPV_IDX and MMMU_PHYS_IDX.
This brings NB_MMU_MODES <= 6, which avoids the TLBs being
reduced in size, which will increase performance.]

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Message-Id: <1475316333-9776-15-git-send-email-atar4qemu@gmail.com>
Signed-off-by: Ricahrd Henderson <rth@twiddle.net>
---
 target-sparc/cpu.h       | 20 ++++++++++++++++----
 target-sparc/translate.c | 18 +++++++++++++-----
 2 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index b0df95f..4309df3 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -223,7 +223,7 @@  enum {
 #if !defined(TARGET_SPARC64)
 #define NB_MMU_MODES 3
 #else
-#define NB_MMU_MODES 7
+#define NB_MMU_MODES 6
 typedef struct trap_state {
     uint64_t tpc;
     uint64_t tnpc;
@@ -665,8 +665,7 @@  int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 #define MMU_KERNEL_IDX 2
 #define MMU_KERNEL_SECONDARY_IDX 3
 #define MMU_NUCLEUS_IDX 4
-#define MMU_HYPV_IDX   5
-#define MMU_PHYS_IDX   6
+#define MMU_PHYS_IDX   5
 #else
 #define MMU_USER_IDX   0
 #define MMU_KERNEL_IDX 1
@@ -688,6 +687,11 @@  static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 {
     return env1->pstate & PS_PRIV;
 }
+#else
+static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+{
+    return env1->psrs;
+}
 #endif
 
 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
@@ -707,7 +711,7 @@  static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
         : (env->lsu & DMMU_E) == 0) {
         return MMU_PHYS_IDX;
     } else if (cpu_hypervisor_mode(env)) {
-        return MMU_HYPV_IDX;
+        return MMU_PHYS_IDX;
     } else if (env->tl > 0) {
         return MMU_NUCLEUS_IDX;
     } else if (cpu_supervisor_mode(env)) {
@@ -755,6 +759,8 @@  trap_state* cpu_tsptr(CPUSPARCState* env);
 #define TB_FLAG_MMU_MASK     7
 #define TB_FLAG_FPU_ENABLED  (1 << 4)
 #define TB_FLAG_AM_ENABLED   (1 << 5)
+#define TB_FLAG_SUPER        (1 << 6)
+#define TB_FLAG_HYPER        (1 << 7)
 #define TB_FLAG_ASI_SHIFT    24
 
 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
@@ -764,7 +770,13 @@  static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
     *pc = env->pc;
     *cs_base = env->npc;
     flags = cpu_mmu_index(env, false);
+    if (cpu_supervisor_mode(env)) {
+        flags |= TB_FLAG_SUPER;
+    }
 #ifdef TARGET_SPARC64
+    if (cpu_hypervisor_mode(env)) {
+        flags |= TB_FLAG_HYPER;
+    }
     if (env->pstate & PS_AM) {
         flags |= TB_FLAG_AM_ENABLED;
     }
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5d7929b..cdec52b 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -72,9 +72,13 @@  typedef struct DisasContext {
     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
     int is_br;
     int mem_idx;
-    int fpu_enabled;
-    int address_mask_32bit;
-    int singlestep;
+    bool fpu_enabled;
+    bool address_mask_32bit;
+    bool singlestep;
+#ifndef CONFIG_USER_ONLY
+    bool supervisor;
+    bool hypervisor;
+#endif
     uint32_t cc_op;  /* current CC operation */
     struct TranslationBlock *tb;
     sparc_def_t *def;
@@ -283,9 +287,9 @@  static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
 #define hypervisor(dc) 0
 #endif
 #else
-#define supervisor(dc) (dc->mem_idx >= MMU_KERNEL_IDX)
+#define supervisor(dc) (dc->supervisor)
 #ifdef TARGET_SPARC64
-#define hypervisor(dc) (dc->mem_idx == MMU_HYPV_IDX)
+#define hypervisor(dc) (dc->hypervisor)
 #else
 #endif
 #endif
@@ -5695,6 +5699,10 @@  void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
     dc->fpu_enabled = tb_fpu_enabled(tb->flags);
     dc->address_mask_32bit = tb_am_enabled(tb->flags);
     dc->singlestep = (cs->singlestep_enabled || singlestep);
+#ifndef CONFIG_USER_ONLY
+    dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
+    dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
+#endif
 #ifdef TARGET_SPARC64
     dc->fprs_dirty = 0;
     dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
-- 
2.7.4