| Message ID | e999e89e-37e4-4b53-7d4f-65bf779eeed2@foss.arm.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Oct 05, 2016 at 05:44:08PM +0100, Jiong Wang wrote: > On 27/09/16 17:03, Jiong Wang wrote: > > > > Now as ARM patches have gone in around r240427, I have done a > quick confirmation > > on the status of these four pending testsuite patches: > > > > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00337.html > > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00338.html > > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00339.html > > https://gcc.gnu.org/ml/gcc-patches/2016-07/msg00340.html > > > > The result is they applies cleanly on gcc trunk, and there is no > regression on > > AArch64 native regression test. Testcases enabled without > requirement of FP16 > > all passed. > > > > I will give a final run on ARM native board and AArch64 emulation > environment > > with ARMv8.2-A FP16 enabled. (Have done this before, just in case > something > > changed during these days) > > > > OK for trunk if there is no regression? > > > > Thanks > > Finished the final tests on emulator with FP16 enabled. > > * No regression on AARCH64, all new testcases passed. > * No regression on AARCH32, part of these new testcases UNRESOLVED > because > they should be skipped on AARCH32, fixed by the attached trivial patch > which I will merge into the 4th patch (no affect on changelog). > > OK to commit these patches? And to be explicit, this is OK too. Thanks for the tests! Cheers, James
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c index f8c8c79..0bebec7 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c index 23c11a4..68ce599 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c index ae4c8b5..1b5a09b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c index 56a6533..766c783 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c index fb54e96..8f5c14b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c index 57c765c..ccfecf4 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c index f9a5bbe..161c7a0 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c index a5997cc..2d3cd8a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c index f0a37e8..0d35385 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c index 41e57a2..ca23e3f 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c index e19eb51..f51cac3 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c index 6d09db9..57901c8 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c index f81c900..3218873 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c index 00f6923..af6a5b6 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcltzh_f16_1.c @@ -1,6 +1,7 @@ /* { dg-do run } */ /* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */ /* { dg-add-options arm_v8_2a_fp16_scalar } */ +/* { dg-skip-if "" { arm*-*-* } } */ #include <arm_fp16.h>