diff mbox

[U-Boot,RFC,5/6] arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to Kconfig

Message ID 1475270352-17225-6-git-send-email-york.sun@nxp.com
State Accepted
Commit fd6381029dc38aad9ab5b69fe1ea5e6efb3745d2
Delegated to: York Sun
Headers show

Commit Message

York Sun Sept. 30, 2016, 9:19 p.m. UTC 
Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.

Signed-off-by: York Sun <york.sun@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig         | 8 ++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 ---
 2 files changed, 8 insertions(+), 3 deletions(-)

Comments

Simon Glass Oct. 3, 2016, 9:49 p.m. UTC | #1 
On 30 September 2016 at 15:19, York Sun <york.sun@nxp.com> wrote:
> Move this option to Kconfig and clean up existing uses.
> NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig         | 8 ++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 ---
>  2 files changed, 8 insertions(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index aa412ec..f683a14 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -45,6 +45,11 @@  config MAX_CPUS
 	  cores, count the reserved ports. This will allocate enough memory
 	  in spin table to properly handle all cores.
 
+config NUM_DDR_CONTROLLERS
+	int "Maximum DDR controllers"
+	default 3 if ARCH_LS2080A
+	default 1
+
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
 	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
@@ -52,4 +57,7 @@  config SYS_FSL_IFC_BANK_COUNT
 	default 4 if ARCH_LS1046A
 	default 8 if ARCH_LS2080A
 
+config SYS_FSL_HAS_DP_DDR
+	bool
+
 endmenu
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 2f10ab7..6ee75cb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -30,8 +30,6 @@ 
 #define CONFIG_SYS_MEM_RESERVE_SECURE	(2048 * 1024)	/* 2MB */
 
 #ifdef CONFIG_LS2080A
-#define CONFIG_NUM_DDR_CONTROLLERS		3
-#define CONFIG_SYS_FSL_HAS_DP_DDR		/* Runtime check to confirm */
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_FSL_SRDS_1
@@ -150,7 +148,6 @@ 
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE		0x00200000 /* 2M */