From patchwork Sat Sep 24 19:20:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 674348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3shL115sttz9s5w for ; Sun, 25 Sep 2016 05:30:29 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=oVljrk70; dkim-atps=neutral Received: from localhost ([::1]:35329 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnseZ-0005Y6-Bb for incoming@patchwork.ozlabs.org; Sat, 24 Sep 2016 15:30:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnsVr-0005QT-SH for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bnsVn-00020E-2C for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:27 -0400 Received: from mail-pa0-f67.google.com ([209.85.220.67]:36613) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnsVm-000206-So for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:22 -0400 Received: by mail-pa0-f67.google.com with SMTP id my20so6601697pab.3 for ; Sat, 24 Sep 2016 12:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bgz43db2FEnsbMtS7jkP6AE1USz2pGoPB6MYAwY6JPI=; b=oVljrk70UccqPLiSO7KzipYYpcyqcMTJceyYYPLvXA8kCKfovErgl7AEYQqXp/a3yn 2IH+Eme8GsjayuYiiSVlKS9EuKXSWko/7pKtph4quVqIJch+HjqArwqQn0MQG2nshgbt xDNhUxIe4faLvyXL69DD9is1tZFk8I4EFo1YM0am1TKshqK79Z++2RFgU+9rS2lzk8AB UPfnI7jMSFx335ZIpledUFOhsZpC0ordp4c/uSk4ov8CUdzjUONifraKU5k6CWYWnD2Q B3ebji50RUb7JupUF4hDK1yFrFbafhk/hF6gXlEp55WBXxfiXhP6JyzPuJT9u0vunjkc e1OA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bgz43db2FEnsbMtS7jkP6AE1USz2pGoPB6MYAwY6JPI=; b=ZuZcIfHLB7VZaHc3xk7g6FYw5mbAFvUAv+G4GXS2aKVGcdbBApQbi8Y+LccRrv/hL/ GBFrWw5mY2qEQMM70fmwAhrepqj9GJrIG+Xq/A5e+yVEUecgpABBtwoWRmrcKC6Jct3c sjAebMlbdRMdnQ1BTazcwZuoEAlfcoX2hx6DumZqqhPaPkvvagkMthJg2lJdkErP+VT3 mekiXeEHiHzqYOQFShgFHIo9xP3ma+ct7DhOZrs/2nwQkKQySZd3lDn1xBJYXwVcxlje qF9vv0Flfmfm2FfmM4Wf2iBddaNdVhHO5xuDR7lAsQLE6w0JMGHMc3xyUNu64A+4/rZx EInQ== X-Gm-Message-State: AE9vXwOAYH/WBXBruU0oQTHO7h2ICZLubHttbSBa3YR9mBa2Yp2aKdvJ0433hPSDhSbsOg== X-Received: by 10.66.254.102 with SMTP id ah6mr23596456pad.59.1474744822452; Sat, 24 Sep 2016 12:20:22 -0700 (PDT) Received: from localhost ([2601:646:8581:937e:696f:1ffa:ab17:d7de]) by smtp.gmail.com with ESMTPSA id jh3sm20246210pac.16.2016.09.24.12.20.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Sep 2016 12:20:22 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sat, 24 Sep 2016 12:20:21 -0700 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.67 Subject: [Qemu-devel] [PATCH v8 7/8] STM32F205: Connect the SPI devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, konstanty@ieee.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Connect the SPI devices to the STM32F205 SoC. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- V2: - Fix up the device/devices commit message hw/arm/stm32f205_soc.c | 22 ++++++++++++++++++++++ include/hw/arm/stm32f205_soc.h | 3 +++ 2 files changed, 25 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 2feddc3..38425bd 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -36,10 +36,13 @@ static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, 0x40012200 }; +static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800, + 0x40003C00 }; static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; #define ADC_IRQ 18 +static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51}; static void stm32f205_soc_initfn(Object *obj) { @@ -68,6 +71,12 @@ static void stm32f205_soc_initfn(Object *obj) TYPE_STM32F2XX_ADC); qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); } + + for (i = 0; i < STM_NUM_SPIS; i++) { + object_initialize(&s->spi[i], sizeof(s->spi[i]), + TYPE_STM32F2XX_SPI); + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); + } } static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -167,6 +176,19 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); } + + /* SPI 1 and 2 */ + for (i = 0; i < STM_NUM_SPIS; i++) { + dev = DEVICE(&(s->spi[i])); + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, spi_irq[i])); + } } static Property stm32f205_soc_properties[] = { diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 1adf824..1332141 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -30,6 +30,7 @@ #include "hw/char/stm32f2xx_usart.h" #include "hw/adc/stm32f2xx_adc.h" #include "hw/or-irq.h" +#include "hw/ssi/stm32f2xx_spi.h" #define TYPE_STM32F205_SOC "stm32f205-soc" #define STM32F205_SOC(obj) \ @@ -38,6 +39,7 @@ #define STM_NUM_USARTS 6 #define STM_NUM_TIMERS 4 #define STM_NUM_ADCS 3 +#define STM_NUM_SPIS 3 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) @@ -56,6 +58,7 @@ typedef struct STM32F205State { STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; STM32F2XXADCState adc[STM_NUM_ADCS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; qemu_or_irq *adc_irqs; } STM32F205State;