From patchwork Sat Sep 24 19:20:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 674347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3shL050G5tz9s5w for ; Sun, 25 Sep 2016 05:29:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ZcRH9/qa; dkim-atps=neutral Received: from localhost ([::1]:35322 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnsdm-0004wU-LS for incoming@patchwork.ozlabs.org; Sat, 24 Sep 2016 15:29:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnsVp-0005Nl-RK for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bnsVj-0001yj-Ow for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:24 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:36327) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bnsVj-0001yA-HZ for qemu-devel@nongnu.org; Sat, 24 Sep 2016 15:21:19 -0400 Received: by mail-pf0-f196.google.com with SMTP id n24so6854505pfb.3 for ; Sat, 24 Sep 2016 12:21:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=izNmEy8vIJ89IdNcoVavO1ra0PpavyiCEZgSi408DWY=; b=ZcRH9/qaI6zuI/h8Hc/W5G76ZDGJ/KpGpueREbFpwNB+DAdCR9dCvqOOBsaoFLXGj2 XeqdK2CZMH0GY8WrEbitbxSQY+dmqO9qFNyoBIS4FrLoURkautKcP5TBFW3SdyF4nna2 DztI6pmkIKmZtlmXTxHv+0P7+pG3mp+csOnwPKNz7kWg1i1Fzo2h9BKKLFq4b3V9KEig HRw5Lt9HUkDBdt0BhAnvuwbIOKw9UT+e/gE/Yzx8iFQavmhk7OfS4PoPgNzf9oK2mSqq m4bDhBuR/uqLoJAcxF71N6A0qqUe99p19wOzHUx3jZ/YUeDp5wC8m8AJQYf/6w6myJ0d Yzcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=izNmEy8vIJ89IdNcoVavO1ra0PpavyiCEZgSi408DWY=; b=XkhIlTojK9JCSJiybIZL0dzd+Cx017mji5gmwBh3FMY8f48GoOaf7EMdCkcFF6mnF3 h2HeJn+3riywYUq7E6AA1xBooZMNcj6Lttny6Awr9x44F6X1SRqtDppV4zZvrqoKGIW+ fbobR/6q2yMUrBqo+mGaO4dLHTLZyB+B9SFf0wRpRxQGaVSHNq2TaFY2vTuIF5ItWrcA Mfi+lJfh1GIVnYTQMlqWB4pWhs3JqSt0cZ5i99chBv1wcYhXCwt2OuvojaBWfcTqySyH I3tl9Qq0c6nf5xIpPx6obqag43RMtKMaZxhFMhjELPvcouC1NKD4oaf1qUGuUfTnt3Tx 6adg== X-Gm-Message-State: AE9vXwNkxEbmdIwf8L91xu5crbA9N7CZWzs/5hNOFzVumMSO9/wzpT42GrAfQS3yB5+snA== X-Received: by 10.98.86.11 with SMTP id k11mr23395664pfb.182.1474744819097; Sat, 24 Sep 2016 12:20:19 -0700 (PDT) Received: from localhost ([2601:646:8581:937e:696f:1ffa:ab17:d7de]) by smtp.gmail.com with ESMTPSA id d4sm20241003paz.20.2016.09.24.12.20.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Sep 2016 12:20:18 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Sat, 24 Sep 2016 12:20:18 -0700 Message-Id: <6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.196 Subject: [Qemu-devel] [PATCH v8 6/8] STM32F205: Connect the ADC devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, konstanty@ieee.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Connect the ADC devices to the STM32F205 SoC. Signed-off-by: Alistair Francis --- V7: - Create the new ADC device V5: - Use the new irq ORing function V4: - Connect all the interrupt lines correctly V2: - Fix up the device/devices commit message hw/arm/stm32f205_soc.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/stm32f205_soc.h | 6 ++++++ 2 files changed, 41 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 5b6fa3b..2feddc3 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -34,9 +34,12 @@ static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400, 0x40000800, 0x40000C00 }; static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400, 0x40004800, 0x40004C00, 0x40005000, 0x40011400 }; +static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100, + 0x40012200 }; static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50}; static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71}; +#define ADC_IRQ 18 static void stm32f205_soc_initfn(Object *obj) { @@ -57,6 +60,14 @@ static void stm32f205_soc_initfn(Object *obj) TYPE_STM32F2XX_TIMER); qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); } + + s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + object_initialize(&s->adc[i], sizeof(s->adc[i]), + TYPE_STM32F2XX_ADC); + qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default()); + } } static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) @@ -132,6 +143,30 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(busdev, 0, timer_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(nvic, timer_irq[i])); } + + /* ADC 1 to 3 */ + object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, + "num-lines", &err); + object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, + qdev_get_gpio_in(nvic, ADC_IRQ)); + + for (i = 0; i < STM_NUM_ADCS; i++) { + dev = DEVICE(&(s->adc[i])); + object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, adc_addr[i]); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); + } } static Property stm32f205_soc_properties[] = { diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h index 779b5da..1adf824 100644 --- a/include/hw/arm/stm32f205_soc.h +++ b/include/hw/arm/stm32f205_soc.h @@ -28,6 +28,8 @@ #include "hw/misc/stm32f2xx_syscfg.h" #include "hw/timer/stm32f2xx_timer.h" #include "hw/char/stm32f2xx_usart.h" +#include "hw/adc/stm32f2xx_adc.h" +#include "hw/or-irq.h" #define TYPE_STM32F205_SOC "stm32f205-soc" #define STM32F205_SOC(obj) \ @@ -35,6 +37,7 @@ #define STM_NUM_USARTS 6 #define STM_NUM_TIMERS 4 +#define STM_NUM_ADCS 3 #define FLASH_BASE_ADDRESS 0x08000000 #define FLASH_SIZE (1024 * 1024) @@ -52,6 +55,9 @@ typedef struct STM32F205State { STM32F2XXSyscfgState syscfg; STM32F2XXUsartState usart[STM_NUM_USARTS]; STM32F2XXTimerState timer[STM_NUM_TIMERS]; + STM32F2XXADCState adc[STM_NUM_ADCS]; + + qemu_or_irq *adc_irqs; } STM32F205State; #endif