| Message ID | 1474617443-11325-2-git-send-email-kever.yang@rock-chips.com |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On 23 September 2016 at 01:57, Kever Yang <kever.yang@rock-chips.com> wrote: > Update PPLL to 676MHz and PMU_PCLK to 48MHz, because: > 1. 48MHz can make sure the pwm can get exact 50% duty ratio, but 99MHz > can not, > 2. We think 48MHz is fast enough for pmu pclk and it is lower power cost > than 99MHz, > 3. PPLL 676 MHz and PMU_PCLK 48MHz are the clock rate we are using > internally for kernel,it suppose not to change the bus clock like pmu_pclk > in kernel, so we want to change it in uboot. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Acked-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v3: None > Changes in v2: None > > arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied to u-boot-rockchip, thanks!
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index c919f47..6776e48 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -64,9 +64,9 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); #define APLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) -#define PPLL_HZ (594*MHz) +#define PPLL_HZ (676*MHz) -#define PMU_PCLK_HZ (99*MHz) +#define PMU_PCLK_HZ (48*MHz) #define ACLKM_CORE_HZ (300*MHz) #define ATCLK_CORE_HZ (300*MHz)