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[U-Boot,8/9] arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1

Message ID 1473924540-30182-1-git-send-email-clsee@altera.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Chin Liang See Sept. 15, 2016, 7:29 a.m. UTC 
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stabil LPDDR2 operation

Signed-off-by: Chin Liang See <clsee@altera.com>
---
 board/terasic/de0-nano-soc/qts/sdram_config.h | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h
index 7084797..75aecda 100644
--- a/board/terasic/de0-nano-soc/qts/sdram_config.h
+++ b/board/terasic/de0-nano-soc/qts/sdram_config.h
@@ -33,6 +33,9 @@ 
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10