| Message ID | 1473924465-29970-1-git-send-email-clsee@altera.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > Same comment as 2/9 Yup, this patch is not required. Thanks Chin Liang > > > Signed-off-by: Chin Liang See <clsee@altera.com> > > --- > > board/denx/mcvevk/qts/sdram_config.h | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/board/denx/mcvevk/qts/sdram_config.h > > b/board/denx/mcvevk/qts/sdram_config.h > > index 30c4d7d..0328850 100644 > > --- a/board/denx/mcvevk/qts/sdram_config.h > > +++ b/board/denx/mcvevk/qts/sdram_config.h > > @@ -49,6 +49,9 @@ > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP > > 5 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT > > 512 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C > > HIP 2 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST > > 0x0 > > > >
On 09/15/2016 09:27 AM, Chin Liang See wrote: > Adding new handoff for SDRAM ctrcfg.extratime1 which is > required for stabil LPDDR2 operation Same comment as 2/9 > Signed-off-by: Chin Liang See <clsee@altera.com> > --- > board/denx/mcvevk/qts/sdram_config.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h > index 30c4d7d..0328850 100644 > --- a/board/denx/mcvevk/qts/sdram_config.h > +++ b/board/denx/mcvevk/qts/sdram_config.h > @@ -49,6 +49,9 @@ > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 >
diff --git a/board/denx/mcvevk/qts/sdram_config.h b/board/denx/mcvevk/qts/sdram_config.h index 30c4d7d..0328850 100644 --- a/board/denx/mcvevk/qts/sdram_config.h +++ b/board/denx/mcvevk/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <clsee@altera.com> --- board/denx/mcvevk/qts/sdram_config.h | 3 +++ 1 file changed, 3 insertions(+)