| Message ID | 1474048017-26696-10-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
Richard Henderson <rth@twiddle.net> writes: > Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > cputlb.c | 21 +++++++++++++++++++++ > softmmu_template.h | 23 ----------------------- > 2 files changed, 21 insertions(+), 23 deletions(-) > > diff --git a/cputlb.c b/cputlb.c > index 5575b73..0c9b77b 100644 > --- a/cputlb.c > +++ b/cputlb.c > @@ -527,6 +527,27 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, > victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ > (ADDR) & TARGET_PAGE_MASK) > > +/* Probe for whether the specified guest write access is permitted. > + * If it is not permitted then an exception will be taken in the same > + * way as if this were a real write access (and we will not return). > + * Otherwise the function will return, and there will be a valid > + * entry in the TLB for this access. > + */ > +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, > + uintptr_t retaddr) > +{ > + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); > + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; > + > + if ((addr & TARGET_PAGE_MASK) > + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { > + /* TLB entry is for a different page */ > + if (!VICTIM_TLB_HIT(addr_write, addr)) { > + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); > + } > + } > +} > + > #define MMUSUFFIX _mmu > > #define DATA_SIZE 1 > diff --git a/softmmu_template.h b/softmmu_template.h > index f9c51fe..538cff5 100644 > --- a/softmmu_template.h > +++ b/softmmu_template.h > @@ -464,29 +464,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, > glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); > } > #endif /* DATA_SIZE > 1 */ > - > -#if DATA_SIZE == 1 > -/* Probe for whether the specified guest write access is permitted. > - * If it is not permitted then an exception will be taken in the same > - * way as if this were a real write access (and we will not return). > - * Otherwise the function will return, and there will be a valid > - * entry in the TLB for this access. > - */ > -void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, > - uintptr_t retaddr) > -{ > - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); > - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; > - > - if ((addr & TARGET_PAGE_MASK) > - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { > - /* TLB entry is for a different page */ > - if (!VICTIM_TLB_HIT(addr_write, addr)) { > - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); > - } > - } > -} > -#endif > #endif /* !defined(SOFTMMU_CODE_ACCESS) */ > > #undef READ_ACCESS_TYPE -- Alex Bennée
diff --git a/cputlb.c b/cputlb.c index 5575b73..0c9b77b 100644 --- a/cputlb.c +++ b/cputlb.c @@ -527,6 +527,27 @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) +/* Probe for whether the specified guest write access is permitted. + * If it is not permitted then an exception will be taken in the same + * way as if this were a real write access (and we will not return). + * Otherwise the function will return, and there will be a valid + * entry in the TLB for this access. + */ +void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, + uintptr_t retaddr) +{ + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + /* TLB entry is for a different page */ + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); + } + } +} + #define MMUSUFFIX _mmu #define DATA_SIZE 1 diff --git a/softmmu_template.h b/softmmu_template.h index f9c51fe..538cff5 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -464,29 +464,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); } #endif /* DATA_SIZE > 1 */ - -#if DATA_SIZE == 1 -/* Probe for whether the specified guest write access is permitted. - * If it is not permitted then an exception will be taken in the same - * way as if this were a real write access (and we will not return). - * Otherwise the function will return, and there will be a valid - * entry in the TLB for this access. - */ -void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, - uintptr_t retaddr) -{ - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - /* TLB entry is for a different page */ - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); - } - } -} -#endif #endif /* !defined(SOFTMMU_CODE_ACCESS) */ #undef READ_ACCESS_TYPE
Signed-off-by: Richard Henderson <rth@twiddle.net> --- cputlb.c | 21 +++++++++++++++++++++ softmmu_template.h | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-)