Patchwork PATCH: PR target/45913: [4.6 Regression] ICE: in insn_default_length, at config/i386/i386.md:584 with -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops

login
register
mail settings
Submitter H.J. Lu
Date Oct. 7, 2010, 2:23 a.m.
Message ID <20101007022318.GA21000@intel.com>
Download mbox | patch
Permalink /patch/66993/
State New
Headers show

Comments

H.J. Lu - Oct. 7, 2010, 2:23 a.m.
Hi,

ix86_binary_operator_ok failed to check "andhi/andsi/anddi" as a
zero-extending move.  OK to install if there are no regressions on
Linux/ia32 and Linux/x86-64?

Thanks.


H.J.
--
gcc/

2010-10-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/45913
	* config/i386/i386.c (ix86_binary_operator_ok): Support
	"andhi/andsi/anddi" as a zero-extending move.

gcc/testsuite/

2010-10-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/45913
	* gcc.target/i386/pr45913.c: New.
Richard Henderson - Oct. 7, 2010, 4:10 p.m.
On 10/06/2010 07:23 PM, H.J. Lu wrote:
> 	PR target/45913
> 	* config/i386/i386.c (ix86_binary_operator_ok): Support
> 	"andhi/andsi/anddi" as a zero-extending move.

Ok.


r~

Patch

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0998f31..b4a5748 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -14987,7 +14987,16 @@  ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
 
   /* Source 1 cannot be a non-matching memory.  */
   if (MEM_P (src1) && !rtx_equal_p (dst, src1))
-    return false;
+    {
+      /* Support "andhi/andsi/anddi" as a zero-extending move.  */
+      return (code == AND
+	      && (mode == HImode
+		  || mode == SImode
+		  || (TARGET_64BIT && mode == DImode))
+	      && CONST_INT_P (src2)
+	      && (INTVAL (src2) == 0xff
+		  || INTVAL (src2) == 0xffff));
+    }
 
   return true;
 }
--- /dev/null	2010-09-15 11:43:08.091350194 -0700
+++ gcc/gcc/testsuite/gcc.target/i386/pr45913.c	2010-10-06 19:05:40.114285874 -0700
@@ -0,0 +1,23 @@ 
+/* PR target/45913 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fselective-scheduling2 -fsel-sched-pipelining -fsel-sched-pipelining-outer-loops" } */
+
+extern void bar (int, int);
+
+int ss[128];
+
+void
+foo (int i, int j, int k, int *p1, int *p2)
+{
+  int s[128];
+  __builtin_memcpy (s, ss, sizeof s);
+
+  while (i--)
+    {
+      int a = s[i];
+      while (j--)
+	bar (k, p2[a]);
+      j = s[i] & 0xFF;
+      bar (p1[a], k);
+    }
+}