Patchwork [11/11] mips: avoid write only variables

login
register
mail settings
Submitter Blue Swirl
Date Oct. 6, 2010, 9:34 p.m.
Message ID <AANLkTik+sX3YdpzYt4D2vVoMZ8jW2i2M3V=9cSXkN4jw@mail.gmail.com>
Download mbox | patch
Permalink /patch/66981/
State New
Headers show

Comments

Blue Swirl - Oct. 6, 2010, 9:34 p.m.
Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
/src/qemu/target-mips/translate.c: In function 'gen_ld':
/src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set
but not used [-Werror=unused-but-set-variable]

Fix by making the variable declarations and uses conditional to debugging.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
---
 target-mips/translate.c | 1222 +++++++++++++++++++++++++----------------------
 1 files changed, 641 insertions(+), 581 deletions(-)

         save_cpu_state(ctx, 1);
@@ -1091,7 +1095,7 @@ static void gen_ld (CPUState *env, DisasContext
*ctx, uint32_t opc,
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_ld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "ldpc";
+        D(opn = "ldpc");
         break;
 #endif
     case OPC_LWPC:
@@ -1100,57 +1104,57 @@ static void gen_ld (CPUState *env,
DisasContext *ctx, uint32_t opc,
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_lw(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lwpc";
+        D(opn = "lwpc");
         break;
     case OPC_LW:
         save_cpu_state(ctx, 0);
         op_ld_lw(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lw";
+        D(opn = "lw");
         break;
     case OPC_LH:
         save_cpu_state(ctx, 0);
         op_ld_lh(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lh";
+        D(opn = "lh");
         break;
     case OPC_LHU:
         save_cpu_state(ctx, 0);
         op_ld_lhu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lhu";
+        D(opn = "lhu");
         break;
     case OPC_LB:
         save_cpu_state(ctx, 0);
         op_ld_lb(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lb";
+        D(opn = "lb");
         break;
     case OPC_LBU:
         save_cpu_state(ctx, 0);
         op_ld_lbu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lbu";
+        D(opn = "lbu");
         break;
     case OPC_LWL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
         gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
-        opn = "lwl";
+        D(opn = "lwl");
         break;
     case OPC_LWR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
         gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
-        opn = "lwr";
+        D(opn = "lwr");
         break;
     case OPC_LL:
         save_cpu_state(ctx, 1);
         op_ld_ll(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "ll";
+        D(opn = "ll");
         break;
     }
     MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
@@ -1162,7 +1166,9 @@ static void gen_ld (CPUState *env, DisasContext
*ctx, uint32_t opc,
 static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
                     int base, int16_t offset)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "st";
+#endif
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();

@@ -1173,43 +1179,43 @@ static void gen_st (DisasContext *ctx,
uint32_t opc, int rt,
     case OPC_SD:
         save_cpu_state(ctx, 0);
         op_st_sd(t1, t0, ctx);
-        opn = "sd";
+        D(opn = "sd");
         break;
     case OPC_SDL:
         save_cpu_state(ctx, 1);
         gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
-        opn = "sdl";
+        D(opn = "sdl");
         break;
     case OPC_SDR:
         save_cpu_state(ctx, 1);
         gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
-        opn = "sdr";
+        D(opn = "sdr");
         break;
 #endif
     case OPC_SW:
         save_cpu_state(ctx, 0);
         op_st_sw(t1, t0, ctx);
-        opn = "sw";
+        D(opn = "sw");
         break;
     case OPC_SH:
         save_cpu_state(ctx, 0);
         op_st_sh(t1, t0, ctx);
-        opn = "sh";
+        D(opn = "sh");
         break;
     case OPC_SB:
         save_cpu_state(ctx, 0);
         op_st_sb(t1, t0, ctx);
-        opn = "sb";
+        D(opn = "sb");
         break;
     case OPC_SWL:
         save_cpu_state(ctx, 1);
         gen_helper_2i(swl, t1, t0, ctx->mem_idx);
-        opn = "swl";
+        D(opn = "swl");
         break;
     case OPC_SWR:
         save_cpu_state(ctx, 1);
         gen_helper_2i(swr, t1, t0, ctx->mem_idx);
-        opn = "swr";
+        D(opn = "swr");
         break;
     }
     MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
@@ -1222,7 +1228,9 @@ static void gen_st (DisasContext *ctx, uint32_t
opc, int rt,
 static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
                          int base, int16_t offset)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "st_cond";
+#endif
     TCGv t0, t1;

     t0 = tcg_temp_local_new();
@@ -1238,13 +1246,13 @@ static void gen_st_cond (DisasContext *ctx,
uint32_t opc, int rt,
     case OPC_SCD:
         save_cpu_state(ctx, 0);
         op_st_scd(t1, t0, rt, ctx);
-        opn = "scd";
+        D(opn = "scd");
         break;
 #endif
     case OPC_SC:
         save_cpu_state(ctx, 1);
         op_st_sc(t1, t0, rt, ctx);
-        opn = "sc";
+        D(opn = "sc");
         break;
     }
     MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
@@ -1256,7 +1264,9 @@ static void gen_st_cond (DisasContext *ctx,
uint32_t opc, int rt,
 static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
                           int base, int16_t offset)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "flt_ldst";
+#endif
     TCGv t0 = tcg_temp_new();

     gen_base_offset_addr(ctx, t0, base, offset);
@@ -1272,7 +1282,7 @@ static void gen_flt_ldst (DisasContext *ctx,
uint32_t opc, int ft,
             gen_store_fpr32(fp0, ft);
             tcg_temp_free_i32(fp0);
         }
-        opn = "lwc1";
+        D(opn = "lwc1");
         break;
     case OPC_SWC1:
         {
@@ -1285,7 +1295,7 @@ static void gen_flt_ldst (DisasContext *ctx,
uint32_t opc, int ft,
             tcg_temp_free(t1);
             tcg_temp_free_i32(fp0);
         }
-        opn = "swc1";
+        D(opn = "swc1");
         break;
     case OPC_LDC1:
         {
@@ -1295,7 +1305,7 @@ static void gen_flt_ldst (DisasContext *ctx,
uint32_t opc, int ft,
             gen_store_fpr64(ctx, fp0, ft);
             tcg_temp_free_i64(fp0);
         }
-        opn = "ldc1";
+        D(opn = "ldc1");
         break;
     case OPC_SDC1:
         {
@@ -1305,7 +1315,7 @@ static void gen_flt_ldst (DisasContext *ctx,
uint32_t opc, int ft,
             tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
             tcg_temp_free_i64(fp0);
         }
-        opn = "sdc1";
+        D(opn = "sdc1");
         break;
     default:
         MIPS_INVAL(opn);
@@ -1333,7 +1343,9 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
                            int rt, int rs, int16_t imm)
 {
     target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "imm arith";
+#endif

     if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
         /* If no destination, treat it as a NOP.
@@ -1366,7 +1378,7 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rt);
             tcg_temp_free(t0);
         }
-        opn = "addi";
+        D(opn = "addi");
         break;
     case OPC_ADDIU:
         if (rs != 0) {
@@ -1375,7 +1387,7 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
         }
-        opn = "addiu";
+        D(opn = "addiu");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DADDI:
@@ -1400,7 +1412,7 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rt);
             tcg_temp_free(t0);
         }
-        opn = "daddi";
+        D(opn = "daddi");
         break;
     case OPC_DADDIU:
         if (rs != 0) {
@@ -1408,7 +1420,7 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
         }
-        opn = "daddiu";
+        D(opn = "daddiu");
         break;
 #endif
     }
@@ -1419,7 +1431,9 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
 static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int
rs, int16_t imm)
 {
     target_ulong uimm;
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "imm logic";
+#endif

     if (rt == 0) {
         /* If no destination, treat it as a NOP. */
@@ -1433,25 +1447,25 @@ static void gen_logic_imm (CPUState *env,
uint32_t opc, int rt, int rs, int16_t
             tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], 0);
-        opn = "andi";
+        D(opn = "andi");
         break;
     case OPC_ORI:
         if (rs != 0)
             tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-        opn = "ori";
+        D(opn = "ori");
         break;
     case OPC_XORI:
         if (likely(rs != 0))
             tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-        opn = "xori";
+        D(opn = "xori");
         break;
     case OPC_LUI:
         tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
-        opn = "lui";
+        D(opn = "lui");
         break;
     }
     MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt],
regnames[rs], uimm);
@@ -1461,7 +1475,9 @@ static void gen_logic_imm (CPUState *env,
uint32_t opc, int rt, int rs, int16_t
 static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs,
int16_t imm)
 {
     target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "imm arith";
+#endif
     TCGv t0;

     if (rt == 0) {
@@ -1474,11 +1490,11 @@ static void gen_slt_imm (CPUState *env,
uint32_t opc, int rt, int rs, int16_t im
     switch (opc) {
     case OPC_SLTI:
         tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
-        opn = "slti";
+        D(opn = "slti");
         break;
     case OPC_SLTIU:
         tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
-        opn = "sltiu";
+        D(opn = "sltiu");
         break;
     }
     MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt],
regnames[rs], uimm);
@@ -1490,7 +1506,9 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
                           int rt, int rs, int16_t imm)
 {
     target_ulong uimm = ((uint16_t)imm) & 0x1f;
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "imm shift";
+#endif
     TCGv t0;

     if (rt == 0) {
@@ -1505,11 +1523,11 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
     case OPC_SLL:
         tcg_gen_shli_tl(t0, t0, uimm);
         tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
-        opn = "sll";
+        D(opn = "sll");
         break;
     case OPC_SRA:
         tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
-        opn = "sra";
+        D(opn = "sra");
         break;
     case OPC_SRL:
         if (uimm != 0) {
@@ -1518,7 +1536,7 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
         }
-        opn = "srl";
+        D(opn = "srl");
         break;
     case OPC_ROTR:
         if (uimm != 0) {
@@ -1531,20 +1549,20 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
         }
-        opn = "rotr";
+        D(opn = "rotr");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DSLL:
         tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
-        opn = "dsll";
+        D(opn = "dsll");
         break;
     case OPC_DSRA:
         tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
-        opn = "dsra";
+        D(opn = "dsra");
         break;
     case OPC_DSRL:
         tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
-        opn = "dsrl";
+        D(opn = "dsrl");
         break;
     case OPC_DROTR:
         if (uimm != 0) {
@@ -1552,23 +1570,23 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_mov_tl(cpu_gpr[rt], t0);
         }
-        opn = "drotr";
+        D(opn = "drotr");
         break;
     case OPC_DSLL32:
         tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
-        opn = "dsll32";
+        D(opn = "dsll32");
         break;
     case OPC_DSRA32:
         tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
-        opn = "dsra32";
+        D(opn = "dsra32");
         break;
     case OPC_DSRL32:
         tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
-        opn = "dsrl32";
+        D(opn = "dsrl32");
         break;
     case OPC_DROTR32:
         tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
-        opn = "drotr32";
+        D(opn = "drotr32");
         break;
 #endif
     }
@@ -1580,7 +1598,9 @@ static void gen_shift_imm(CPUState *env,
DisasContext *ctx, uint32_t opc,
 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
                        int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "arith";
+#endif

     if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
        && opc != OPC_DADD && opc != OPC_DSUB) {
@@ -1614,7 +1634,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rd);
             tcg_temp_free(t0);
         }
-        opn = "add";
+        D(opn = "add");
         break;
     case OPC_ADDU:
         if (rs != 0 && rt != 0) {
@@ -1627,7 +1647,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "addu";
+        D(opn = "addu");
         break;
     case OPC_SUB:
         {
@@ -1652,7 +1672,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rd);
             tcg_temp_free(t0);
         }
-        opn = "sub";
+        D(opn = "sub");
         break;
     case OPC_SUBU:
         if (rs != 0 && rt != 0) {
@@ -1666,7 +1686,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "subu";
+        D(opn = "subu");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DADD:
@@ -1691,7 +1711,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rd);
             tcg_temp_free(t0);
         }
-        opn = "dadd";
+        D(opn = "dadd");
         break;
     case OPC_DADDU:
         if (rs != 0 && rt != 0) {
@@ -1703,7 +1723,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "daddu";
+        D(opn = "daddu");
         break;
     case OPC_DSUB:
         {
@@ -1727,7 +1747,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
             gen_store_gpr(t0, rd);
             tcg_temp_free(t0);
         }
-        opn = "dsub";
+        D(opn = "dsub");
         break;
     case OPC_DSUBU:
         if (rs != 0 && rt != 0) {
@@ -1739,7 +1759,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "dsubu";
+        D(opn = "dsubu");
         break;
 #endif
     case OPC_MUL:
@@ -1749,7 +1769,7 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "mul";
+        D(opn = "mul");
         break;
     }
     MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
@@ -1758,7 +1778,9 @@ static void gen_arith (CPUState *env,
DisasContext *ctx, uint32_t opc,
 /* Conditional move */
 static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "cond move";
+#endif
     int l1;

     if (rd == 0) {
@@ -1775,12 +1797,12 @@ static void gen_cond_move (CPUState *env,
uint32_t opc, int rd, int rs, int rt)
             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1);
         else
             tcg_gen_br(l1);
-        opn = "movn";
+        D(opn = "movn");
         break;
     case OPC_MOVZ:
         if (likely(rt != 0))
             tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1);
-        opn = "movz";
+        D(opn = "movz");
         break;
     }
     if (rs != 0)
@@ -1795,7 +1817,9 @@ static void gen_cond_move (CPUState *env,
uint32_t opc, int rd, int rs, int rt)
 /* Logic */
 static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "logic";
+#endif

     if (rd == 0) {
         /* If no destination, treat it as a NOP. */
@@ -1810,7 +1834,7 @@ static void gen_logic (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "and";
+        D(opn = "and");
         break;
     case OPC_NOR:
         if (rs != 0 && rt != 0) {
@@ -1822,7 +1846,7 @@ static void gen_logic (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
         }
-        opn = "nor";
+        D(opn = "nor");
         break;
     case OPC_OR:
         if (likely(rs != 0 && rt != 0)) {
@@ -1834,7 +1858,7 @@ static void gen_logic (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "or";
+        D(opn = "or");
         break;
     case OPC_XOR:
         if (likely(rs != 0 && rt != 0)) {
@@ -1846,7 +1870,7 @@ static void gen_logic (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
         } else {
             tcg_gen_movi_tl(cpu_gpr[rd], 0);
         }
-        opn = "xor";
+        D(opn = "xor");
         break;
     }
     MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
@@ -1855,7 +1879,9 @@ static void gen_logic (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
 /* Set on lower than */
 static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "slt";
+#endif
     TCGv t0, t1;

     if (rd == 0) {
@@ -1871,11 +1897,11 @@ static void gen_slt (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
     switch (opc) {
     case OPC_SLT:
         tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
-        opn = "slt";
+        D(opn = "slt");
         break;
     case OPC_SLTU:
         tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
-        opn = "sltu";
+        D(opn = "sltu");
         break;
     }
     MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
@@ -1887,7 +1913,9 @@ static void gen_slt (CPUState *env, uint32_t
opc, int rd, int rs, int rt)
 static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
                        int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "shifts";
+#endif
     TCGv t0, t1;

     if (rd == 0) {
@@ -1906,19 +1934,19 @@ static void gen_shift (CPUState *env,
DisasContext *ctx, uint32_t opc,
         tcg_gen_andi_tl(t0, t0, 0x1f);
         tcg_gen_shl_tl(t0, t1, t0);
         tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
-        opn = "sllv";
+        D(opn = "sllv");
         break;
     case OPC_SRAV:
         tcg_gen_andi_tl(t0, t0, 0x1f);
         tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
-        opn = "srav";
+        D(opn = "srav");
         break;
     case OPC_SRLV:
         tcg_gen_ext32u_tl(t1, t1);
         tcg_gen_andi_tl(t0, t0, 0x1f);
         tcg_gen_shr_tl(t0, t1, t0);
         tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
-        opn = "srlv";
+        D(opn = "srlv");
         break;
     case OPC_ROTRV:
         {
@@ -1932,29 +1960,29 @@ static void gen_shift (CPUState *env,
DisasContext *ctx, uint32_t opc,
             tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
             tcg_temp_free_i32(t2);
             tcg_temp_free_i32(t3);
-            opn = "rotrv";
+            D(opn = "rotrv");
         }
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DSLLV:
         tcg_gen_andi_tl(t0, t0, 0x3f);
         tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
-        opn = "dsllv";
+        D(opn = "dsllv");
         break;
     case OPC_DSRAV:
         tcg_gen_andi_tl(t0, t0, 0x3f);
         tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
-        opn = "dsrav";
+        D(opn = "dsrav");
         break;
     case OPC_DSRLV:
         tcg_gen_andi_tl(t0, t0, 0x3f);
         tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
-        opn = "dsrlv";
+        D(opn = "dsrlv");
         break;
     case OPC_DROTRV:
         tcg_gen_andi_tl(t0, t0, 0x3f);
         tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
-        opn = "drotrv";
+        D(opn = "drotrv");
         break;
 #endif
     }
@@ -1966,7 +1994,9 @@ static void gen_shift (CPUState *env,
DisasContext *ctx, uint32_t opc,
 /* Arithmetic on HI/LO registers */
 static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "hilo";
+#endif

     if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
         /* Treat as NOP. */
@@ -1976,25 +2006,25 @@ static void gen_HILO (DisasContext *ctx,
uint32_t opc, int reg)
     switch (opc) {
     case OPC_MFHI:
         tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
-        opn = "mfhi";
+        D(opn = "mfhi");
         break;
     case OPC_MFLO:
         tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
-        opn = "mflo";
+        D(opn = "mflo");
         break;
     case OPC_MTHI:
         if (reg != 0)
             tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
         else
             tcg_gen_movi_tl(cpu_HI[0], 0);
-        opn = "mthi";
+        D(opn = "mthi");
         break;
     case OPC_MTLO:
         if (reg != 0)
             tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
         else
             tcg_gen_movi_tl(cpu_LO[0], 0);
-        opn = "mtlo";
+        D(opn = "mtlo");
         break;
     }
     MIPS_DEBUG("%s %s", opn, regnames[reg]);
@@ -2003,7 +2033,9 @@ static void gen_HILO (DisasContext *ctx,
uint32_t opc, int reg)
 static void gen_muldiv (DisasContext *ctx, uint32_t opc,
                         int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "mul/div";
+#endif
     TCGv t0, t1;

     switch (opc) {
@@ -2046,7 +2078,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
             gen_set_label(l1);
         }
-        opn = "div";
+        D(opn = "div");
         break;
     case OPC_DIVU:
         {
@@ -2061,7 +2093,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
             gen_set_label(l1);
         }
-        opn = "divu";
+        D(opn = "divu");
         break;
     case OPC_MULT:
         {
@@ -2079,7 +2111,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "mult";
+        D(opn = "mult");
         break;
     case OPC_MULTU:
         {
@@ -2099,7 +2131,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "multu";
+        D(opn = "multu");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DDIV:
@@ -2118,7 +2150,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_rem_i64(cpu_HI[0], t0, t1);
             gen_set_label(l1);
         }
-        opn = "ddiv";
+        D(opn = "ddiv");
         break;
     case OPC_DDIVU:
         {
@@ -2129,15 +2161,15 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_remu_i64(cpu_HI[0], t0, t1);
             gen_set_label(l1);
         }
-        opn = "ddivu";
+        D(opn = "ddivu");
         break;
     case OPC_DMULT:
         gen_helper_dmult(t0, t1);
-        opn = "dmult";
+        D(opn = "dmult");
         break;
     case OPC_DMULTU:
         gen_helper_dmultu(t0, t1);
-        opn = "dmultu";
+        D(opn = "dmultu");
         break;
 #endif
     case OPC_MADD:
@@ -2158,7 +2190,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "madd";
+        D(opn = "madd");
         break;
     case OPC_MADDU:
        {
@@ -2180,7 +2212,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "maddu";
+        D(opn = "maddu");
         break;
     case OPC_MSUB:
         {
@@ -2200,7 +2232,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "msub";
+        D(opn = "msub");
         break;
     case OPC_MSUBU:
         {
@@ -2222,7 +2254,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_LO[0], t0);
             tcg_gen_ext32s_tl(cpu_HI[0], t1);
         }
-        opn = "msubu";
+        D(opn = "msubu");
         break;
     default:
         MIPS_INVAL(opn);
@@ -2238,7 +2270,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
                             int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "mul vr54xx";
+#endif
     TCGv t0 = tcg_temp_new();
     TCGv t1 = tcg_temp_new();

@@ -2248,59 +2282,59 @@ static void gen_mul_vr54xx (DisasContext *ctx,
uint32_t opc,
     switch (opc) {
     case OPC_VR54XX_MULS:
         gen_helper_muls(t0, t0, t1);
-        opn = "muls";
+        D(opn = "muls");
         break;
     case OPC_VR54XX_MULSU:
         gen_helper_mulsu(t0, t0, t1);
-        opn = "mulsu";
+        D(opn = "mulsu");
         break;
     case OPC_VR54XX_MACC:
         gen_helper_macc(t0, t0, t1);
-        opn = "macc";
+        D(opn = "macc");
         break;
     case OPC_VR54XX_MACCU:
         gen_helper_maccu(t0, t0, t1);
-        opn = "maccu";
+        D(opn = "maccu");
         break;
     case OPC_VR54XX_MSAC:
         gen_helper_msac(t0, t0, t1);
-        opn = "msac";
+        D(opn = "msac");
         break;
     case OPC_VR54XX_MSACU:
         gen_helper_msacu(t0, t0, t1);
-        opn = "msacu";
+        D(opn = "msacu");
         break;
     case OPC_VR54XX_MULHI:
         gen_helper_mulhi(t0, t0, t1);
-        opn = "mulhi";
+        D(opn = "mulhi");
         break;
     case OPC_VR54XX_MULHIU:
         gen_helper_mulhiu(t0, t0, t1);
-        opn = "mulhiu";
+        D(opn = "mulhiu");
         break;
     case OPC_VR54XX_MULSHI:
         gen_helper_mulshi(t0, t0, t1);
-        opn = "mulshi";
+        D(opn = "mulshi");
         break;
     case OPC_VR54XX_MULSHIU:
         gen_helper_mulshiu(t0, t0, t1);
-        opn = "mulshiu";
+        D(opn = "mulshiu");
         break;
     case OPC_VR54XX_MACCHI:
         gen_helper_macchi(t0, t0, t1);
-        opn = "macchi";
+        D(opn = "macchi");
         break;
     case OPC_VR54XX_MACCHIU:
         gen_helper_macchiu(t0, t0, t1);
-        opn = "macchiu";
+        D(opn = "macchiu");
         break;
     case OPC_VR54XX_MSACHI:
         gen_helper_msachi(t0, t0, t1);
-        opn = "msachi";
+        D(opn = "msachi");
         break;
     case OPC_VR54XX_MSACHIU:
         gen_helper_msachiu(t0, t0, t1);
-        opn = "msachiu";
+        D(opn = "msachiu");
         break;
     default:
         MIPS_INVAL("mul vr54xx");
@@ -2318,7 +2352,9 @@ static void gen_mul_vr54xx (DisasContext *ctx,
uint32_t opc,
 static void gen_cl (DisasContext *ctx, uint32_t opc,
                     int rd, int rs)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "CLx";
+#endif
     TCGv t0;

     if (rd == 0) {
@@ -2331,20 +2367,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
     switch (opc) {
     case OPC_CLO:
         gen_helper_clo(cpu_gpr[rd], t0);
-        opn = "clo";
+        D(opn = "clo");
         break;
     case OPC_CLZ:
         gen_helper_clz(cpu_gpr[rd], t0);
-        opn = "clz";
+        D(opn = "clz");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DCLO:
         gen_helper_dclo(cpu_gpr[rd], t0);
-        opn = "dclo";
+        D(opn = "dclo");
         break;
     case OPC_DCLZ:
         gen_helper_dclz(cpu_gpr[rd], t0);
-        opn = "dclz";
+        D(opn = "dclz");
         break;
 #endif
     }
@@ -2356,7 +2392,9 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
 static void gen_loongson_integer (DisasContext *ctx, uint32_t opc,
                                 int rd, int rs, int rt)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "loongson";
+#endif
     TCGv t0, t1;

     if (rd == 0) {
@@ -2393,7 +2431,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
     case OPC_MULT_G_2F:
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
         tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
-        opn = "mult.g";
+        D(opn = "mult.g");
         break;
     case OPC_MULTU_G_2E:
     case OPC_MULTU_G_2F:
@@ -2401,7 +2439,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
         tcg_gen_ext32u_tl(t1, t1);
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
         tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
-        opn = "multu.g";
+        D(opn = "multu.g");
         break;
     case OPC_DIV_G_2E:
     case OPC_DIV_G_2F:
@@ -2424,7 +2462,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
             gen_set_label(l3);
         }
-        opn = "div.g";
+        D(opn = "div.g");
         break;
     case OPC_DIVU_G_2E:
     case OPC_DIVU_G_2F:
@@ -2441,7 +2479,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
             gen_set_label(l2);
         }
-        opn = "divu.g";
+        D(opn = "divu.g");
         break;
     case OPC_MOD_G_2E:
     case OPC_MOD_G_2F:
@@ -2462,7 +2500,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
             gen_set_label(l3);
         }
-        opn = "mod.g";
+        D(opn = "mod.g");
         break;
     case OPC_MODU_G_2E:
     case OPC_MODU_G_2F:
@@ -2479,18 +2517,18 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
             gen_set_label(l2);
         }
-        opn = "modu.g";
+        D(opn = "modu.g");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DMULT_G_2E:
     case OPC_DMULT_G_2F:
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
-        opn = "dmult.g";
+        D(opn = "dmult.g");
         break;
     case OPC_DMULTU_G_2E:
     case OPC_DMULTU_G_2F:
         tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
-        opn = "dmultu.g";
+        D(opn = "dmultu.g");
         break;
     case OPC_DDIV_G_2E:
     case OPC_DDIV_G_2F:
@@ -2510,7 +2548,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
             gen_set_label(l3);
         }
-        opn = "ddiv.g";
+        D(opn = "ddiv.g");
         break;
     case OPC_DDIVU_G_2E:
     case OPC_DDIVU_G_2F:
@@ -2524,7 +2562,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
             gen_set_label(l2);
         }
-        opn = "ddivu.g";
+        D(opn = "ddivu.g");
         break;
     case OPC_DMOD_G_2E:
     case OPC_DMOD_G_2F:
@@ -2542,7 +2580,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
             gen_set_label(l3);
         }
-        opn = "dmod.g";
+        D(opn = "dmod.g");
         break;
     case OPC_DMODU_G_2E:
     case OPC_DMODU_G_2F:
@@ -2556,7 +2594,7 @@ static void gen_loongson_integer (DisasContext
*ctx, uint32_t opc,
             tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
             gen_set_label(l2);
         }
-        opn = "dmodu.g";
+        D(opn = "dmodu.g");
         break;
 #endif
     }
@@ -3163,7 +3201,9 @@ static inline void gen_mtc0_store64 (TCGv arg,
target_ulong off)

 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int
reg, int sel)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *rn = "invalid";
+#endif

     if (sel != 0)
         check_insn(env, ctx, ISA_MIPS32);
@@ -3173,22 +3213,22 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
-            rn = "Index";
+            D(rn = "Index");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpcontrol(arg);
-            rn = "MVPControl";
+            D(rn = "MVPControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpconf0(arg);
-            rn = "MVPConf0";
+            D(rn = "MVPConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpconf1(arg);
-            rn = "MVPConf1";
+            D(rn = "MVPConf1");
             break;
         default:
             goto die;
@@ -3198,42 +3238,42 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mfc0_random(arg);
-            rn = "Random";
+            D(rn = "Random");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
-            rn = "VPEControl";
+            D(rn = "VPEControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
-            rn = "VPEConf0";
+            D(rn = "VPEConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
-            rn = "VPEConf1";
+            D(rn = "VPEConf1");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
-            rn = "YQMask";
+            D(rn = "YQMask");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
-            rn = "VPESchedule";
+            D(rn = "VPESchedule");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
-            rn = "VPEScheFBack";
+            D(rn = "VPEScheFBack");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
-            rn = "VPEOpt";
+            D(rn = "VPEOpt");
             break;
         default:
             goto die;
@@ -3244,42 +3284,42 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "EntryLo0";
+            D(rn = "EntryLo0");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcstatus(arg);
-            rn = "TCStatus";
+            D(rn = "TCStatus");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcbind(arg);
-            rn = "TCBind";
+            D(rn = "TCBind");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcrestart(arg);
-            rn = "TCRestart";
+            D(rn = "TCRestart");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tchalt(arg);
-            rn = "TCHalt";
+            D(rn = "TCHalt");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tccontext(arg);
-            rn = "TCContext";
+            D(rn = "TCContext");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcschedule(arg);
-            rn = "TCSchedule";
+            D(rn = "TCSchedule");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcschefback(arg);
-            rn = "TCScheFBack";
+            D(rn = "TCScheFBack");
             break;
         default:
             goto die;
@@ -3290,7 +3330,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "EntryLo1";
+            D(rn = "EntryLo1");
             break;
         default:
             goto die;
@@ -3301,11 +3341,11 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "Context";
+            D(rn = "Context");
             break;
         case 1:
 //            gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
-            rn = "ContextConfig";
+            D(rn = "ContextConfig");
 //            break;
         default:
             goto die;
@@ -3315,12 +3355,12 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
-            rn = "PageMask";
+            D(rn = "PageMask");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
-            rn = "PageGrain";
+            D(rn = "PageGrain");
             break;
         default:
             goto die;
@@ -3330,32 +3370,32 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
-            rn = "Wired";
+            D(rn = "Wired");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
-            rn = "SRSConf0";
+            D(rn = "SRSConf0");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
-            rn = "SRSConf1";
+            D(rn = "SRSConf1");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
-            rn = "SRSConf2";
+            D(rn = "SRSConf2");
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
-            rn = "SRSConf3";
+            D(rn = "SRSConf3");
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
-            rn = "SRSConf4";
+            D(rn = "SRSConf4");
             break;
         default:
             goto die;
@@ -3366,7 +3406,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
-            rn = "HWREna";
+            D(rn = "HWREna");
             break;
         default:
             goto die;
@@ -3377,7 +3417,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "BadVAddr";
+            D(rn = "BadVAddr");
             break;
         default:
             goto die;
@@ -3394,7 +3434,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
                 gen_io_end();
                 ctx->bstate = BS_STOP;
             }
-            rn = "Count";
+            D(rn = "Count");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -3406,7 +3446,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "EntryHi";
+            D(rn = "EntryHi");
             break;
         default:
             goto die;
@@ -3416,7 +3456,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
-            rn = "Compare";
+            D(rn = "Compare");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -3427,22 +3467,22 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
-            rn = "Status";
+            D(rn = "Status");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
-            rn = "IntCtl";
+            D(rn = "IntCtl");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
-            rn = "SRSCtl";
+            D(rn = "SRSCtl");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
-            rn = "SRSMap";
+            D(rn = "SRSMap");
             break;
         default:
             goto die;
@@ -3452,7 +3492,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
-            rn = "Cause";
+            D(rn = "Cause");
             break;
         default:
             goto die;
@@ -3463,7 +3503,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "EPC";
+            D(rn = "EPC");
             break;
         default:
             goto die;
@@ -3473,12 +3513,12 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
-            rn = "PRid";
+            D(rn = "PRid");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
-            rn = "EBase";
+            D(rn = "EBase");
             break;
         default:
             goto die;
@@ -3488,29 +3528,29 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
-            rn = "Config";
+            D(rn = "Config");
             break;
         case 1:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
-            rn = "Config1";
+            D(rn = "Config1");
             break;
         case 2:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
-            rn = "Config2";
+            D(rn = "Config2");
             break;
         case 3:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
-            rn = "Config3";
+            D(rn = "Config3");
             break;
         /* 4,5 are reserved */
         /* 6,7 are implementation dependent */
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
-            rn = "Config6";
+            D(rn = "Config6");
             break;
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
-            rn = "Config7";
+            D(rn = "Config7");
             break;
         default:
             goto die;
@@ -3520,7 +3560,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mfc0_lladdr(arg);
-            rn = "LLAddr";
+            D(rn = "LLAddr");
             break;
         default:
             goto die;
@@ -3530,7 +3570,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mfc0_watchlo, arg, sel);
-            rn = "WatchLo";
+            D(rn = "WatchLo");
             break;
         default:
             goto die;
@@ -3540,7 +3580,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0 ...7:
             gen_helper_1i(mfc0_watchhi, arg, sel);
-            rn = "WatchHi";
+            D(rn = "WatchHi");
             break;
         default:
             goto die;
@@ -3553,7 +3593,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
             check_insn(env, ctx, ISA_MIPS3);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "XContext";
+            D(rn = "XContext");
             break;
 #endif
         default:
@@ -3565,7 +3605,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
-            rn = "Framemask";
+            D(rn = "Framemask");
             break;
         default:
             goto die;
@@ -3573,29 +3613,29 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         break;
     case 22:
         tcg_gen_movi_tl(arg, 0); /* unimplemented */
-        rn = "'Diagnostic"; /* implementation dependent */
+        D(rn = "'Diagnostic"); /* implementation dependent */
         break;
     case 23:
         switch (sel) {
         case 0:
             gen_helper_mfc0_debug(arg); /* EJTAG support */
-            rn = "Debug";
+            D(rn = "Debug");
             break;
         case 1:
 //            gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
-            rn = "TraceControl";
+            D(rn = "TraceControl");
 //            break;
         case 2:
 //            gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
-            rn = "TraceControl2";
+            D(rn = "TraceControl2");
 //            break;
         case 3:
 //            gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
-            rn = "UserTraceData";
+            D(rn = "UserTraceData");
 //            break;
         case 4:
 //            gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
-            rn = "TraceBPC";
+            D(rn = "TraceBPC");
 //            break;
         default:
             goto die;
@@ -3607,7 +3647,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
             /* EJTAG support */
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "DEPC";
+            D(rn = "DEPC");
             break;
         default:
             goto die;
@@ -3617,35 +3657,35 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
-            rn = "Performance0";
+            D(rn = "Performance0");
             break;
         case 1:
 //            gen_helper_mfc0_performance1(arg);
-            rn = "Performance1";
+            D(rn = "Performance1");
 //            break;
         case 2:
 //            gen_helper_mfc0_performance2(arg);
-            rn = "Performance2";
+            D(rn = "Performance2");
 //            break;
         case 3:
 //            gen_helper_mfc0_performance3(arg);
-            rn = "Performance3";
+            D(rn = "Performance3");
 //            break;
         case 4:
 //            gen_helper_mfc0_performance4(arg);
-            rn = "Performance4";
+            D(rn = "Performance4");
 //            break;
         case 5:
 //            gen_helper_mfc0_performance5(arg);
-            rn = "Performance5";
+            D(rn = "Performance5");
 //            break;
         case 6:
 //            gen_helper_mfc0_performance6(arg);
-            rn = "Performance6";
+            D(rn = "Performance6");
 //            break;
         case 7:
 //            gen_helper_mfc0_performance7(arg);
-            rn = "Performance7";
+            D(rn = "Performance7");
 //            break;
         default:
             goto die;
@@ -3653,13 +3693,13 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         break;
     case 26:
         tcg_gen_movi_tl(arg, 0); /* unimplemented */
-        rn = "ECC";
+        D(rn = "ECC");
         break;
     case 27:
         switch (sel) {
         case 0 ... 3:
             tcg_gen_movi_tl(arg, 0); /* unimplemented */
-            rn = "CacheErr";
+            D(rn = "CacheErr");
             break;
         default:
             goto die;
@@ -3672,14 +3712,14 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 4:
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
-            rn = "TagLo";
+            D(rn = "TagLo");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
-            rn = "DataLo";
+            D(rn = "DataLo");
             break;
         default:
             goto die;
@@ -3692,14 +3732,14 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 4:
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
-            rn = "TagHi";
+            D(rn = "TagHi");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
-            rn = "DataHi";
+            D(rn = "DataHi");
             break;
         default:
             goto die;
@@ -3710,7 +3750,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
             tcg_gen_ext32s_tl(arg, arg);
-            rn = "ErrorEPC";
+            D(rn = "ErrorEPC");
             break;
         default:
             goto die;
@@ -3721,7 +3761,7 @@ static void gen_mfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             /* EJTAG support */
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
-            rn = "DESAVE";
+            D(rn = "DESAVE");
             break;
         default:
             goto die;
@@ -3740,7 +3780,9 @@ die:

 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int
reg, int sel)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *rn = "invalid";
+#endif

     if (sel != 0)
         check_insn(env, ctx, ISA_MIPS32);
@@ -3753,22 +3795,22 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_index(arg);
-            rn = "Index";
+            D(rn = "Index");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_mvpcontrol(arg);
-            rn = "MVPControl";
+            D(rn = "MVPControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             /* ignored */
-            rn = "MVPConf0";
+            D(rn = "MVPConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             /* ignored */
-            rn = "MVPConf1";
+            D(rn = "MVPConf1");
             break;
         default:
             goto die;
@@ -3778,42 +3820,42 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             /* ignored */
-            rn = "Random";
+            D(rn = "Random");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpecontrol(arg);
-            rn = "VPEControl";
+            D(rn = "VPEControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeconf0(arg);
-            rn = "VPEConf0";
+            D(rn = "VPEConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeconf1(arg);
-            rn = "VPEConf1";
+            D(rn = "VPEConf1");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_yqmask(arg);
-            rn = "YQMask";
+            D(rn = "YQMask");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
-            rn = "VPESchedule";
+            D(rn = "VPESchedule");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
-            rn = "VPEScheFBack";
+            D(rn = "VPEScheFBack");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeopt(arg);
-            rn = "VPEOpt";
+            D(rn = "VPEOpt");
             break;
         default:
             goto die;
@@ -3823,42 +3865,42 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_entrylo0(arg);
-            rn = "EntryLo0";
+            D(rn = "EntryLo0");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcstatus(arg);
-            rn = "TCStatus";
+            D(rn = "TCStatus");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcbind(arg);
-            rn = "TCBind";
+            D(rn = "TCBind");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcrestart(arg);
-            rn = "TCRestart";
+            D(rn = "TCRestart");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tchalt(arg);
-            rn = "TCHalt";
+            D(rn = "TCHalt");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tccontext(arg);
-            rn = "TCContext";
+            D(rn = "TCContext");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcschedule(arg);
-            rn = "TCSchedule";
+            D(rn = "TCSchedule");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcschefback(arg);
-            rn = "TCScheFBack";
+            D(rn = "TCScheFBack");
             break;
         default:
             goto die;
@@ -3868,7 +3910,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_entrylo1(arg);
-            rn = "EntryLo1";
+            D(rn = "EntryLo1");
             break;
         default:
             goto die;
@@ -3878,11 +3920,11 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_context(arg);
-            rn = "Context";
+            D(rn = "Context");
             break;
         case 1:
 //            gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
-            rn = "ContextConfig";
+            D(rn = "ContextConfig");
 //            break;
         default:
             goto die;
@@ -3892,12 +3934,12 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_pagemask(arg);
-            rn = "PageMask";
+            D(rn = "PageMask");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(arg);
-            rn = "PageGrain";
+            D(rn = "PageGrain");
             break;
         default:
             goto die;
@@ -3907,32 +3949,32 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_wired(arg);
-            rn = "Wired";
+            D(rn = "Wired");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf0(arg);
-            rn = "SRSConf0";
+            D(rn = "SRSConf0");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf1(arg);
-            rn = "SRSConf1";
+            D(rn = "SRSConf1");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf2(arg);
-            rn = "SRSConf2";
+            D(rn = "SRSConf2");
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf3(arg);
-            rn = "SRSConf3";
+            D(rn = "SRSConf3");
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf4(arg);
-            rn = "SRSConf4";
+            D(rn = "SRSConf4");
             break;
         default:
             goto die;
@@ -3943,7 +3985,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_hwrena(arg);
-            rn = "HWREna";
+            D(rn = "HWREna");
             break;
         default:
             goto die;
@@ -3951,13 +3993,13 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         break;
     case 8:
         /* ignored */
-        rn = "BadVAddr";
+        D(rn = "BadVAddr");
         break;
     case 9:
         switch (sel) {
         case 0:
             gen_helper_mtc0_count(arg);
-            rn = "Count";
+            D(rn = "Count");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -3968,7 +4010,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_entryhi(arg);
-            rn = "EntryHi";
+            D(rn = "EntryHi");
             break;
         default:
             goto die;
@@ -3978,7 +4020,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_compare(arg);
-            rn = "Compare";
+            D(rn = "Compare");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -3993,28 +4035,28 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
-            rn = "Status";
+            D(rn = "Status");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_intctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "IntCtl";
+            D(rn = "IntCtl");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "SRSCtl";
+            D(rn = "SRSCtl");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "SRSMap";
+            D(rn = "SRSMap");
             break;
         default:
             goto die;
@@ -4025,7 +4067,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             save_cpu_state(ctx, 1);
             gen_helper_mtc0_cause(arg);
-            rn = "Cause";
+            D(rn = "Cause");
             break;
         default:
             goto die;
@@ -4035,7 +4077,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
-            rn = "EPC";
+            D(rn = "EPC");
             break;
         default:
             goto die;
@@ -4045,12 +4087,12 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             /* ignored */
-            rn = "PRid";
+            D(rn = "PRid");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_ebase(arg);
-            rn = "EBase";
+            D(rn = "EBase");
             break;
         default:
             goto die;
@@ -4060,36 +4102,36 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_config0(arg);
-            rn = "Config";
+            D(rn = "Config");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 1:
             /* ignored, read only */
-            rn = "Config1";
+            D(rn = "Config1");
             break;
         case 2:
             gen_helper_mtc0_config2(arg);
-            rn = "Config2";
+            D(rn = "Config2");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 3:
             /* ignored, read only */
-            rn = "Config3";
+            D(rn = "Config3");
             break;
         /* 4,5 are reserved */
         /* 6,7 are implementation dependent */
         case 6:
             /* ignored */
-            rn = "Config6";
+            D(rn = "Config6");
             break;
         case 7:
             /* ignored */
-            rn = "Config7";
+            D(rn = "Config7");
             break;
         default:
-            rn = "Invalid config selector";
+            D(rn = "Invalid config selector");
             goto die;
         }
         break;
@@ -4097,7 +4139,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_lladdr(arg);
-            rn = "LLAddr";
+            D(rn = "LLAddr");
             break;
         default:
             goto die;
@@ -4107,7 +4149,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mtc0_watchlo, arg, sel);
-            rn = "WatchLo";
+            D(rn = "WatchLo");
             break;
         default:
             goto die;
@@ -4117,7 +4159,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mtc0_watchhi, arg, sel);
-            rn = "WatchHi";
+            D(rn = "WatchHi");
             break;
         default:
             goto die;
@@ -4129,7 +4171,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
 #if defined(TARGET_MIPS64)
             check_insn(env, ctx, ISA_MIPS3);
             gen_helper_mtc0_xcontext(arg);
-            rn = "XContext";
+            D(rn = "XContext");
             break;
 #endif
         default:
@@ -4141,7 +4183,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_framemask(arg);
-            rn = "Framemask";
+            D(rn = "Framemask");
             break;
         default:
             goto die;
@@ -4149,7 +4191,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         break;
     case 22:
         /* ignored */
-        rn = "Diagnostic"; /* implementation dependent */
+        D(rn = "Diagnostic"); /* implementation dependent */
         break;
     case 23:
         switch (sel) {
@@ -4158,17 +4200,17 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
-            rn = "Debug";
+            D(rn = "Debug");
             break;
         case 1:
 //            gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
-            rn = "TraceControl";
+            D(rn = "TraceControl");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
         case 2:
 //            gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
-            rn = "TraceControl2";
+            D(rn = "TraceControl2");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
@@ -4176,7 +4218,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
-            rn = "UserTraceData";
+            D(rn = "UserTraceData");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
@@ -4184,7 +4226,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
 //            gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "TraceBPC";
+            D(rn = "TraceBPC");
 //            break;
         default:
             goto die;
@@ -4195,7 +4237,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             /* EJTAG support */
             gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
-            rn = "DEPC";
+            D(rn = "DEPC");
             break;
         default:
             goto die;
@@ -4205,35 +4247,35 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_helper_mtc0_performance0(arg);
-            rn = "Performance0";
+            D(rn = "Performance0");
             break;
         case 1:
 //            gen_helper_mtc0_performance1(arg);
-            rn = "Performance1";
+            D(rn = "Performance1");
 //            break;
         case 2:
 //            gen_helper_mtc0_performance2(arg);
-            rn = "Performance2";
+            D(rn = "Performance2");
 //            break;
         case 3:
 //            gen_helper_mtc0_performance3(arg);
-            rn = "Performance3";
+            D(rn = "Performance3");
 //            break;
         case 4:
 //            gen_helper_mtc0_performance4(arg);
-            rn = "Performance4";
+            D(rn = "Performance4");
 //            break;
         case 5:
 //            gen_helper_mtc0_performance5(arg);
-            rn = "Performance5";
+            D(rn = "Performance5");
 //            break;
         case 6:
 //            gen_helper_mtc0_performance6(arg);
-            rn = "Performance6";
+            D(rn = "Performance6");
 //            break;
         case 7:
 //            gen_helper_mtc0_performance7(arg);
-            rn = "Performance7";
+            D(rn = "Performance7");
 //            break;
         default:
             goto die;
@@ -4241,13 +4283,13 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
        break;
     case 26:
         /* ignored */
-        rn = "ECC";
+        D(rn = "ECC");
         break;
     case 27:
         switch (sel) {
         case 0 ... 3:
             /* ignored */
-            rn = "CacheErr";
+            D(rn = "CacheErr");
             break;
         default:
             goto die;
@@ -4260,14 +4302,14 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 4:
         case 6:
             gen_helper_mtc0_taglo(arg);
-            rn = "TagLo";
+            D(rn = "TagLo");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_helper_mtc0_datalo(arg);
-            rn = "DataLo";
+            D(rn = "DataLo");
             break;
         default:
             goto die;
@@ -4280,17 +4322,17 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 4:
         case 6:
             gen_helper_mtc0_taghi(arg);
-            rn = "TagHi";
+            D(rn = "TagHi");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_helper_mtc0_datahi(arg);
-            rn = "DataHi";
+            D(rn = "DataHi");
             break;
         default:
-            rn = "invalid sel";
+            D(rn = "invalid sel");
             goto die;
         }
        break;
@@ -4298,7 +4340,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         switch (sel) {
         case 0:
             gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
-            rn = "ErrorEPC";
+            D(rn = "ErrorEPC");
             break;
         default:
             goto die;
@@ -4309,7 +4351,7 @@ static void gen_mtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int s
         case 0:
             /* EJTAG support */
             gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
-            rn = "DESAVE";
+            D(rn = "DESAVE");
             break;
         default:
             goto die;
@@ -4336,7 +4378,9 @@ die:
 #if defined(TARGET_MIPS64)
 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg,
int reg, int sel)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *rn = "invalid";
+#endif

     if (sel != 0)
         check_insn(env, ctx, ISA_MIPS64);
@@ -4346,22 +4390,22 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
-            rn = "Index";
+            D(rn = "Index");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpcontrol(arg);
-            rn = "MVPControl";
+            D(rn = "MVPControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpconf0(arg);
-            rn = "MVPConf0";
+            D(rn = "MVPConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_mvpconf1(arg);
-            rn = "MVPConf1";
+            D(rn = "MVPConf1");
             break;
         default:
             goto die;
@@ -4371,42 +4415,42 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mfc0_random(arg);
-            rn = "Random";
+            D(rn = "Random");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
-            rn = "VPEControl";
+            D(rn = "VPEControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
-            rn = "VPEConf0";
+            D(rn = "VPEConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
-            rn = "VPEConf1";
+            D(rn = "VPEConf1");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
-            rn = "YQMask";
+            D(rn = "YQMask");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
-            rn = "VPESchedule";
+            D(rn = "VPESchedule");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
-            rn = "VPEScheFBack";
+            D(rn = "VPEScheFBack");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
-            rn = "VPEOpt";
+            D(rn = "VPEOpt");
             break;
         default:
             goto die;
@@ -4416,42 +4460,42 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
-            rn = "EntryLo0";
+            D(rn = "EntryLo0");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcstatus(arg);
-            rn = "TCStatus";
+            D(rn = "TCStatus");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mfc0_tcbind(arg);
-            rn = "TCBind";
+            D(rn = "TCBind");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_dmfc0_tcrestart(arg);
-            rn = "TCRestart";
+            D(rn = "TCRestart");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_dmfc0_tchalt(arg);
-            rn = "TCHalt";
+            D(rn = "TCHalt");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_helper_dmfc0_tccontext(arg);
-            rn = "TCContext";
+            D(rn = "TCContext");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_helper_dmfc0_tcschedule(arg);
-            rn = "TCSchedule";
+            D(rn = "TCSchedule");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_dmfc0_tcschefback(arg);
-            rn = "TCScheFBack";
+            D(rn = "TCScheFBack");
             break;
         default:
             goto die;
@@ -4461,7 +4505,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
-            rn = "EntryLo1";
+            D(rn = "EntryLo1");
             break;
         default:
             goto die;
@@ -4471,11 +4515,11 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
-            rn = "Context";
+            D(rn = "Context");
             break;
         case 1:
 //            gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
-            rn = "ContextConfig";
+            D(rn = "ContextConfig");
 //            break;
         default:
             goto die;
@@ -4485,12 +4529,12 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
-            rn = "PageMask";
+            D(rn = "PageMask");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
-            rn = "PageGrain";
+            D(rn = "PageGrain");
             break;
         default:
             goto die;
@@ -4500,32 +4544,32 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
-            rn = "Wired";
+            D(rn = "Wired");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
-            rn = "SRSConf0";
+            D(rn = "SRSConf0");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
-            rn = "SRSConf1";
+            D(rn = "SRSConf1");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
-            rn = "SRSConf2";
+            D(rn = "SRSConf2");
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
-            rn = "SRSConf3";
+            D(rn = "SRSConf3");
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
-            rn = "SRSConf4";
+            D(rn = "SRSConf4");
             break;
         default:
             goto die;
@@ -4536,7 +4580,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
-            rn = "HWREna";
+            D(rn = "HWREna");
             break;
         default:
             goto die;
@@ -4546,7 +4590,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
-            rn = "BadVAddr";
+            D(rn = "BadVAddr");
             break;
         default:
             goto die;
@@ -4563,7 +4607,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
                 gen_io_end();
                 ctx->bstate = BS_STOP;
             }
-            rn = "Count";
+            D(rn = "Count");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -4574,7 +4618,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
-            rn = "EntryHi";
+            D(rn = "EntryHi");
             break;
         default:
             goto die;
@@ -4584,7 +4628,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
-            rn = "Compare";
+            D(rn = "Compare");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -4595,22 +4639,22 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
-            rn = "Status";
+            D(rn = "Status");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
-            rn = "IntCtl";
+            D(rn = "IntCtl");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
-            rn = "SRSCtl";
+            D(rn = "SRSCtl");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
-            rn = "SRSMap";
+            D(rn = "SRSMap");
             break;
         default:
             goto die;
@@ -4620,7 +4664,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
-            rn = "Cause";
+            D(rn = "Cause");
             break;
         default:
             goto die;
@@ -4630,7 +4674,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
-            rn = "EPC";
+            D(rn = "EPC");
             break;
         default:
             goto die;
@@ -4640,12 +4684,12 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
-            rn = "PRid";
+            D(rn = "PRid");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
-            rn = "EBase";
+            D(rn = "EBase");
             break;
         default:
             goto die;
@@ -4655,28 +4699,28 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
-            rn = "Config";
+            D(rn = "Config");
             break;
         case 1:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
-            rn = "Config1";
+            D(rn = "Config1");
             break;
         case 2:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
-            rn = "Config2";
+            D(rn = "Config2");
             break;
         case 3:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
-            rn = "Config3";
+            D(rn = "Config3");
             break;
        /* 6,7 are implementation dependent */
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
-            rn = "Config6";
+            D(rn = "Config6");
             break;
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
-            rn = "Config7";
+            D(rn = "Config7");
             break;
         default:
             goto die;
@@ -4686,7 +4730,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_dmfc0_lladdr(arg);
-            rn = "LLAddr";
+            D(rn = "LLAddr");
             break;
         default:
             goto die;
@@ -4696,7 +4740,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(dmfc0_watchlo, arg, sel);
-            rn = "WatchLo";
+            D(rn = "WatchLo");
             break;
         default:
             goto die;
@@ -4706,7 +4750,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mfc0_watchhi, arg, sel);
-            rn = "WatchHi";
+            D(rn = "WatchHi");
             break;
         default:
             goto die;
@@ -4717,7 +4761,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             check_insn(env, ctx, ISA_MIPS3);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
-            rn = "XContext";
+            D(rn = "XContext");
             break;
         default:
             goto die;
@@ -4728,7 +4772,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
-            rn = "Framemask";
+            D(rn = "Framemask");
             break;
         default:
             goto die;
@@ -4736,29 +4780,29 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         break;
     case 22:
         tcg_gen_movi_tl(arg, 0); /* unimplemented */
-        rn = "'Diagnostic"; /* implementation dependent */
+        D(rn = "'Diagnostic"); /* implementation dependent */
         break;
     case 23:
         switch (sel) {
         case 0:
             gen_helper_mfc0_debug(arg); /* EJTAG support */
-            rn = "Debug";
+            D(rn = "Debug");
             break;
         case 1:
 //            gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
-            rn = "TraceControl";
+            D(rn = "TraceControl");
 //            break;
         case 2:
 //            gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
-            rn = "TraceControl2";
+            D(rn = "TraceControl2");
 //            break;
         case 3:
 //            gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
-            rn = "UserTraceData";
+            D(rn = "UserTraceData");
 //            break;
         case 4:
 //            gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
-            rn = "TraceBPC";
+            D(rn = "TraceBPC");
 //            break;
         default:
             goto die;
@@ -4769,7 +4813,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             /* EJTAG support */
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
-            rn = "DEPC";
+            D(rn = "DEPC");
             break;
         default:
             goto die;
@@ -4779,35 +4823,35 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
-            rn = "Performance0";
+            D(rn = "Performance0");
             break;
         case 1:
 //            gen_helper_dmfc0_performance1(arg);
-            rn = "Performance1";
+            D(rn = "Performance1");
 //            break;
         case 2:
 //            gen_helper_dmfc0_performance2(arg);
-            rn = "Performance2";
+            D(rn = "Performance2");
 //            break;
         case 3:
 //            gen_helper_dmfc0_performance3(arg);
-            rn = "Performance3";
+            D(rn = "Performance3");
 //            break;
         case 4:
 //            gen_helper_dmfc0_performance4(arg);
-            rn = "Performance4";
+            D(rn = "Performance4");
 //            break;
         case 5:
 //            gen_helper_dmfc0_performance5(arg);
-            rn = "Performance5";
+            D(rn = "Performance5");
 //            break;
         case 6:
 //            gen_helper_dmfc0_performance6(arg);
-            rn = "Performance6";
+            D(rn = "Performance6");
 //            break;
         case 7:
 //            gen_helper_dmfc0_performance7(arg);
-            rn = "Performance7";
+            D(rn = "Performance7");
 //            break;
         default:
             goto die;
@@ -4815,14 +4859,14 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         break;
     case 26:
         tcg_gen_movi_tl(arg, 0); /* unimplemented */
-        rn = "ECC";
+        D(rn = "ECC");
         break;
     case 27:
         switch (sel) {
         /* ignored */
         case 0 ... 3:
             tcg_gen_movi_tl(arg, 0); /* unimplemented */
-            rn = "CacheErr";
+            D(rn = "CacheErr");
             break;
         default:
             goto die;
@@ -4835,14 +4879,14 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 4:
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
-            rn = "TagLo";
+            D(rn = "TagLo");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
-            rn = "DataLo";
+            D(rn = "DataLo");
             break;
         default:
             goto die;
@@ -4855,14 +4899,14 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 4:
         case 6:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
-            rn = "TagHi";
+            D(rn = "TagHi");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
-            rn = "DataHi";
+            D(rn = "DataHi");
             break;
         default:
             goto die;
@@ -4872,7 +4916,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
-            rn = "ErrorEPC";
+            D(rn = "ErrorEPC");
             break;
         default:
             goto die;
@@ -4883,7 +4927,7 @@ static void gen_dmfc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             /* EJTAG support */
             gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
-            rn = "DESAVE";
+            D(rn = "DESAVE");
             break;
         default:
             goto die;
@@ -4902,7 +4946,9 @@ die:

 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg,
int reg, int sel)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *rn = "invalid";
+#endif

     if (sel != 0)
         check_insn(env, ctx, ISA_MIPS64);
@@ -4915,22 +4961,22 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_index(arg);
-            rn = "Index";
+            D(rn = "Index");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_mvpcontrol(arg);
-            rn = "MVPControl";
+            D(rn = "MVPControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             /* ignored */
-            rn = "MVPConf0";
+            D(rn = "MVPConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             /* ignored */
-            rn = "MVPConf1";
+            D(rn = "MVPConf1");
             break;
         default:
             goto die;
@@ -4940,42 +4986,42 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             /* ignored */
-            rn = "Random";
+            D(rn = "Random");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpecontrol(arg);
-            rn = "VPEControl";
+            D(rn = "VPEControl");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeconf0(arg);
-            rn = "VPEConf0";
+            D(rn = "VPEConf0");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeconf1(arg);
-            rn = "VPEConf1";
+            D(rn = "VPEConf1");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_yqmask(arg);
-            rn = "YQMask";
+            D(rn = "YQMask");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
-            rn = "VPESchedule";
+            D(rn = "VPESchedule");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
-            rn = "VPEScheFBack";
+            D(rn = "VPEScheFBack");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_vpeopt(arg);
-            rn = "VPEOpt";
+            D(rn = "VPEOpt");
             break;
         default:
             goto die;
@@ -4985,42 +5031,42 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_entrylo0(arg);
-            rn = "EntryLo0";
+            D(rn = "EntryLo0");
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcstatus(arg);
-            rn = "TCStatus";
+            D(rn = "TCStatus");
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcbind(arg);
-            rn = "TCBind";
+            D(rn = "TCBind");
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcrestart(arg);
-            rn = "TCRestart";
+            D(rn = "TCRestart");
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tchalt(arg);
-            rn = "TCHalt";
+            D(rn = "TCHalt");
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tccontext(arg);
-            rn = "TCContext";
+            D(rn = "TCContext");
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcschedule(arg);
-            rn = "TCSchedule";
+            D(rn = "TCSchedule");
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
             gen_helper_mtc0_tcschefback(arg);
-            rn = "TCScheFBack";
+            D(rn = "TCScheFBack");
             break;
         default:
             goto die;
@@ -5030,7 +5076,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_entrylo1(arg);
-            rn = "EntryLo1";
+            D(rn = "EntryLo1");
             break;
         default:
             goto die;
@@ -5040,11 +5086,11 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_context(arg);
-            rn = "Context";
+            D(rn = "Context");
             break;
         case 1:
 //           gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
-            rn = "ContextConfig";
+            D(rn = "ContextConfig");
 //           break;
         default:
             goto die;
@@ -5054,12 +5100,12 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_pagemask(arg);
-            rn = "PageMask";
+            D(rn = "PageMask");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(arg);
-            rn = "PageGrain";
+            D(rn = "PageGrain");
             break;
         default:
             goto die;
@@ -5069,32 +5115,32 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_wired(arg);
-            rn = "Wired";
+            D(rn = "Wired");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf0(arg);
-            rn = "SRSConf0";
+            D(rn = "SRSConf0");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf1(arg);
-            rn = "SRSConf1";
+            D(rn = "SRSConf1");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf2(arg);
-            rn = "SRSConf2";
+            D(rn = "SRSConf2");
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf3(arg);
-            rn = "SRSConf3";
+            D(rn = "SRSConf3");
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf4(arg);
-            rn = "SRSConf4";
+            D(rn = "SRSConf4");
             break;
         default:
             goto die;
@@ -5105,7 +5151,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_hwrena(arg);
-            rn = "HWREna";
+            D(rn = "HWREna");
             break;
         default:
             goto die;
@@ -5113,13 +5159,13 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         break;
     case 8:
         /* ignored */
-        rn = "BadVAddr";
+        D(rn = "BadVAddr");
         break;
     case 9:
         switch (sel) {
         case 0:
             gen_helper_mtc0_count(arg);
-            rn = "Count";
+            D(rn = "Count");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -5132,7 +5178,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_entryhi(arg);
-            rn = "EntryHi";
+            D(rn = "EntryHi");
             break;
         default:
             goto die;
@@ -5142,7 +5188,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_compare(arg);
-            rn = "Compare";
+            D(rn = "Compare");
             break;
         /* 6,7 are implementation dependent */
         default:
@@ -5159,28 +5205,28 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
-            rn = "Status";
+            D(rn = "Status");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_intctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "IntCtl";
+            D(rn = "IntCtl");
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsctl(arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "SRSCtl";
+            D(rn = "SRSCtl");
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "SRSMap";
+            D(rn = "SRSMap");
             break;
         default:
             goto die;
@@ -5201,7 +5247,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
             }
             /* Stop translation as we may have triggered an intetrupt */
             ctx->bstate = BS_STOP;
-            rn = "Cause";
+            D(rn = "Cause");
             break;
         default:
             goto die;
@@ -5211,7 +5257,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
-            rn = "EPC";
+            D(rn = "EPC");
             break;
         default:
             goto die;
@@ -5221,12 +5267,12 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             /* ignored */
-            rn = "PRid";
+            D(rn = "PRid");
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
             gen_helper_mtc0_ebase(arg);
-            rn = "EBase";
+            D(rn = "EBase");
             break;
         default:
             goto die;
@@ -5236,27 +5282,27 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_config0(arg);
-            rn = "Config";
+            D(rn = "Config");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 1:
             /* ignored, read only */
-            rn = "Config1";
+            D(rn = "Config1");
             break;
         case 2:
             gen_helper_mtc0_config2(arg);
-            rn = "Config2";
+            D(rn = "Config2");
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 3:
             /* ignored */
-            rn = "Config3";
+            D(rn = "Config3");
             break;
         /* 6,7 are implementation dependent */
         default:
-            rn = "Invalid config selector";
+            D(rn = "Invalid config selector");
             goto die;
         }
         break;
@@ -5264,7 +5310,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_lladdr(arg);
-            rn = "LLAddr";
+            D(rn = "LLAddr");
             break;
         default:
             goto die;
@@ -5274,7 +5320,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mtc0_watchlo, arg, sel);
-            rn = "WatchLo";
+            D(rn = "WatchLo");
             break;
         default:
             goto die;
@@ -5284,7 +5330,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0 ... 7:
             gen_helper_1i(mtc0_watchhi, arg, sel);
-            rn = "WatchHi";
+            D(rn = "WatchHi");
             break;
         default:
             goto die;
@@ -5295,7 +5341,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             check_insn(env, ctx, ISA_MIPS3);
             gen_helper_mtc0_xcontext(arg);
-            rn = "XContext";
+            D(rn = "XContext");
             break;
         default:
             goto die;
@@ -5306,7 +5352,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_framemask(arg);
-            rn = "Framemask";
+            D(rn = "Framemask");
             break;
         default:
             goto die;
@@ -5314,7 +5360,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         break;
     case 22:
         /* ignored */
-        rn = "Diagnostic"; /* implementation dependent */
+        D(rn = "Diagnostic"); /* implementation dependent */
         break;
     case 23:
         switch (sel) {
@@ -5323,31 +5369,31 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
-            rn = "Debug";
+            D(rn = "Debug");
             break;
         case 1:
 //            gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "TraceControl";
+            D(rn = "TraceControl");
 //            break;
         case 2:
 //            gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "TraceControl2";
+            D(rn = "TraceControl2");
 //            break;
         case 3:
 //            gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "UserTraceData";
+            D(rn = "UserTraceData");
 //            break;
         case 4:
 //            gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-            rn = "TraceBPC";
+            D(rn = "TraceBPC");
 //            break;
         default:
             goto die;
@@ -5358,7 +5404,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             /* EJTAG support */
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
-            rn = "DEPC";
+            D(rn = "DEPC");
             break;
         default:
             goto die;
@@ -5368,35 +5414,35 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             gen_helper_mtc0_performance0(arg);
-            rn = "Performance0";
+            D(rn = "Performance0");
             break;
         case 1:
 //            gen_helper_mtc0_performance1(arg);
-            rn = "Performance1";
+            D(rn = "Performance1");
 //            break;
         case 2:
 //            gen_helper_mtc0_performance2(arg);
-            rn = "Performance2";
+            D(rn = "Performance2");
 //            break;
         case 3:
 //            gen_helper_mtc0_performance3(arg);
-            rn = "Performance3";
+            D(rn = "Performance3");
 //            break;
         case 4:
 //            gen_helper_mtc0_performance4(arg);
-            rn = "Performance4";
+            D(rn = "Performance4");
 //            break;
         case 5:
 //            gen_helper_mtc0_performance5(arg);
-            rn = "Performance5";
+            D(rn = "Performance5");
 //            break;
         case 6:
 //            gen_helper_mtc0_performance6(arg);
-            rn = "Performance6";
+            D(rn = "Performance6");
 //            break;
         case 7:
 //            gen_helper_mtc0_performance7(arg);
-            rn = "Performance7";
+            D(rn = "Performance7");
 //            break;
         default:
             goto die;
@@ -5404,13 +5450,13 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         break;
     case 26:
         /* ignored */
-        rn = "ECC";
+        D(rn = "ECC");
         break;
     case 27:
         switch (sel) {
         case 0 ... 3:
             /* ignored */
-            rn = "CacheErr";
+            D(rn = "CacheErr");
             break;
         default:
             goto die;
@@ -5423,14 +5469,14 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 4:
         case 6:
             gen_helper_mtc0_taglo(arg);
-            rn = "TagLo";
+            D(rn = "TagLo");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_helper_mtc0_datalo(arg);
-            rn = "DataLo";
+            D(rn = "DataLo");
             break;
         default:
             goto die;
@@ -5443,17 +5489,17 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 4:
         case 6:
             gen_helper_mtc0_taghi(arg);
-            rn = "TagHi";
+            D(rn = "TagHi");
             break;
         case 1:
         case 3:
         case 5:
         case 7:
             gen_helper_mtc0_datahi(arg);
-            rn = "DataHi";
+            D(rn = "DataHi");
             break;
         default:
-            rn = "invalid sel";
+            D(rn = "invalid sel");
             goto die;
         }
         break;
@@ -5461,7 +5507,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         switch (sel) {
         case 0:
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
-            rn = "ErrorEPC";
+            D(rn = "ErrorEPC");
             break;
         default:
             goto die;
@@ -5472,7 +5518,7 @@ static void gen_dmtc0 (CPUState *env,
DisasContext *ctx, TCGv arg, int reg, int
         case 0:
             /* EJTAG support */
             gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
-            rn = "DESAVE";
+            D(rn = "DESAVE");
             break;
         default:
             goto die;
@@ -5827,7 +5873,9 @@ die:

 static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc,
int rt, int rd)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "ldst";
+#endif

     switch (opc) {
     case OPC_MFC0:
@@ -5836,7 +5884,7 @@ static void gen_cp0 (CPUState *env, DisasContext
*ctx, uint32_t opc, int rt, int
             return;
         }
         gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
-        opn = "mfc0";
+        D(opn = "mfc0");
         break;
     case OPC_MTC0:
         {
@@ -5846,7 +5894,7 @@ static void gen_cp0 (CPUState *env, DisasContext
*ctx, uint32_t opc, int rt, int
             gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
             tcg_temp_free(t0);
         }
-        opn = "mtc0";
+        D(opn = "mtc0");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DMFC0:
@@ -5856,7 +5904,7 @@ static void gen_cp0 (CPUState *env, DisasContext
*ctx, uint32_t opc, int rt, int
             return;
         }
         gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
-        opn = "dmfc0";
+        D(opn = "dmfc0");
         break;
     case OPC_DMTC0:
         check_insn(env, ctx, ISA_MIPS3);
@@ -5867,7 +5915,7 @@ static void gen_cp0 (CPUState *env, DisasContext
*ctx, uint32_t opc, int rt, int
             gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7);
             tcg_temp_free(t0);
         }
-        opn = "dmtc0";
+        D(opn = "dmtc0");
         break;
 #endif
     case OPC_MFTR:
@@ -5878,46 +5926,46 @@ static void gen_cp0 (CPUState *env,
DisasContext *ctx, uint32_t opc, int rt, int
         }
         gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
                  ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
-        opn = "mftr";
+        D(opn = "mftr");
         break;
     case OPC_MTTR:
         check_insn(env, ctx, ASE_MT);
         gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
                  ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
-        opn = "mttr";
+        D(opn = "mttr");
         break;
     case OPC_TLBWI:
-        opn = "tlbwi";
+        D(opn = "tlbwi");
         if (!env->tlb->helper_tlbwi)
             goto die;
         gen_helper_tlbwi();
         break;
     case OPC_TLBWR:
-        opn = "tlbwr";
+        D(opn = "tlbwr");
         if (!env->tlb->helper_tlbwr)
             goto die;
         gen_helper_tlbwr();
         break;
     case OPC_TLBP:
-        opn = "tlbp";
+        D(opn = "tlbp");
         if (!env->tlb->helper_tlbp)
             goto die;
         gen_helper_tlbp();
         break;
     case OPC_TLBR:
-        opn = "tlbr";
+        D(opn = "tlbr");
         if (!env->tlb->helper_tlbr)
             goto die;
         gen_helper_tlbr();
         break;
     case OPC_ERET:
-        opn = "eret";
+        D(opn = "eret");
         check_insn(env, ctx, ISA_MIPS2);
         gen_helper_eret();
         ctx->bstate = BS_EXCP;
         break;
     case OPC_DERET:
-        opn = "deret";
+        D(opn = "deret");
         check_insn(env, ctx, ISA_MIPS32);
         if (!(ctx->hflags & MIPS_HFLAG_DM)) {
             MIPS_INVAL(opn);
@@ -5928,7 +5976,7 @@ static void gen_cp0 (CPUState *env, DisasContext
*ctx, uint32_t opc, int rt, int
         }
         break;
     case OPC_WAIT:
-        opn = "wait";
+        D(opn = "wait");
         check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
         /* If we get an exception, we want to restart at next instruction */
         ctx->pc += 4;
@@ -5952,7 +6000,9 @@ static void gen_compute_branch1 (CPUState *env,
DisasContext *ctx, uint32_t op,
                                  int32_t cc, int32_t offset)
 {
     target_ulong btarget;
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "cp1 cond branch";
+#endif
     TCGv_i32 t0 = tcg_temp_new_i32();

     if (cc != 0)
@@ -5966,26 +6016,26 @@ static void gen_compute_branch1 (CPUState
*env, DisasContext *ctx, uint32_t op,
         tcg_gen_not_i32(t0, t0);
         tcg_gen_andi_i32(t0, t0, 1);
         tcg_gen_extu_i32_tl(bcond, t0);
-        opn = "bc1f";
+        D(opn = "bc1f");
         goto not_likely;
     case OPC_BC1FL:
         tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
         tcg_gen_not_i32(t0, t0);
         tcg_gen_andi_i32(t0, t0, 1);
         tcg_gen_extu_i32_tl(bcond, t0);
-        opn = "bc1fl";
+        D(opn = "bc1fl");
         goto likely;
     case OPC_BC1T:
         tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
         tcg_gen_andi_i32(t0, t0, 1);
         tcg_gen_extu_i32_tl(bcond, t0);
-        opn = "bc1t";
+        D(opn = "bc1t");
         goto not_likely;
     case OPC_BC1TL:
         tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
         tcg_gen_andi_i32(t0, t0, 1);
         tcg_gen_extu_i32_tl(bcond, t0);
-        opn = "bc1tl";
+        D(opn = "bc1tl");
     likely:
         ctx->hflags |= MIPS_HFLAG_BL;
         break;
@@ -5999,7 +6049,7 @@ static void gen_compute_branch1 (CPUState *env,
DisasContext *ctx, uint32_t op,
             tcg_gen_andi_i32(t0, t0, 1);
             tcg_gen_extu_i32_tl(bcond, t0);
         }
-        opn = "bc1any2f";
+        D(opn = "bc1any2f");
         goto not_likely;
     case OPC_BC1TANY2:
         {
@@ -6011,7 +6061,7 @@ static void gen_compute_branch1 (CPUState *env,
DisasContext *ctx, uint32_t op,
             tcg_gen_andi_i32(t0, t0, 1);
             tcg_gen_extu_i32_tl(bcond, t0);
         }
-        opn = "bc1any2t";
+        D(opn = "bc1any2t");
         goto not_likely;
     case OPC_BC1FANY4:
         {
@@ -6027,7 +6077,7 @@ static void gen_compute_branch1 (CPUState *env,
DisasContext *ctx, uint32_t op,
             tcg_gen_andi_i32(t0, t0, 1);
             tcg_gen_extu_i32_tl(bcond, t0);
         }
-        opn = "bc1any4f";
+        D(opn = "bc1any4f");
         goto not_likely;
     case OPC_BC1TANY4:
         {
@@ -6043,7 +6093,7 @@ static void gen_compute_branch1 (CPUState *env,
DisasContext *ctx, uint32_t op,
             tcg_gen_andi_i32(t0, t0, 1);
             tcg_gen_extu_i32_tl(bcond, t0);
         }
-        opn = "bc1any4t";
+        D(opn = "bc1any4t");
     not_likely:
         ctx->hflags |= MIPS_HFLAG_BC;
         break;
@@ -6206,7 +6256,9 @@ enum fopcode {

 static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "cp1 move";
+#endif
     TCGv t0 = tcg_temp_new();

     switch (opc) {
@@ -6219,7 +6271,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t
opc, int rt, int fs)
             tcg_temp_free_i32(fp0);
         }
         gen_store_gpr(t0, rt);
-        opn = "mfc1";
+        D(opn = "mfc1");
         break;
     case OPC_MTC1:
         gen_load_gpr(t0, rt);
@@ -6230,28 +6282,28 @@ static void gen_cp1 (DisasContext *ctx,
uint32_t opc, int rt, int fs)
             gen_store_fpr32(fp0, fs);
             tcg_temp_free_i32(fp0);
         }
-        opn = "mtc1";
+        D(opn = "mtc1");
         break;
     case OPC_CFC1:
         gen_helper_1i(cfc1, t0, fs);
         gen_store_gpr(t0, rt);
-        opn = "cfc1";
+        D(opn = "cfc1");
         break;
     case OPC_CTC1:
         gen_load_gpr(t0, rt);
         gen_helper_1i(ctc1, t0, fs);
-        opn = "ctc1";
+        D(opn = "ctc1");
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DMFC1:
         gen_load_fpr64(ctx, t0, fs);
         gen_store_gpr(t0, rt);
-        opn = "dmfc1";
+        D(opn = "dmfc1");
         break;
     case OPC_DMTC1:
         gen_load_gpr(t0, rt);
         gen_store_fpr64(ctx, t0, fs);
-        opn = "dmtc1";
+        D(opn = "dmtc1");
         break;
 #endif
     case OPC_MFHC1:
@@ -6263,7 +6315,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t
opc, int rt, int fs)
             tcg_temp_free_i32(fp0);
         }
         gen_store_gpr(t0, rt);
-        opn = "mfhc1";
+        D(opn = "mfhc1");
         break;
     case OPC_MTHC1:
         gen_load_gpr(t0, rt);
@@ -6274,7 +6326,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t
opc, int rt, int fs)
             gen_store_fpr32h(fp0, fs);
             tcg_temp_free_i32(fp0);
         }
-        opn = "mthc1";
+        D(opn = "mthc1");
         break;
     default:
         MIPS_INVAL(opn);
@@ -6387,6 +6439,7 @@ static inline void gen_movcf_ps (int fs, int fd,
int cc, int tf)
 static void gen_farith (DisasContext *ctx, enum fopcode op1,
                         int ft, int fs, int fd, int cc)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "farith";
     const char *condnames[] = {
             "c.f",
@@ -6424,6 +6477,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             "cabs.le",
             "cabs.ngt",
     };
+#endif
     enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP;
     uint32_t func = ctx->opcode & 0x3f;

@@ -6440,7 +6494,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "add.s";
+        D(opn = "add.s");
         optype = BINOP;
         break;
     case OPC_SUB_S:
@@ -6455,7 +6509,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "sub.s";
+        D(opn = "sub.s");
         optype = BINOP;
         break;
     case OPC_MUL_S:
@@ -6470,7 +6524,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "mul.s";
+        D(opn = "mul.s");
         optype = BINOP;
         break;
     case OPC_DIV_S:
@@ -6485,7 +6539,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "div.s";
+        D(opn = "div.s");
         optype = BINOP;
         break;
     case OPC_SQRT_S:
@@ -6497,7 +6551,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "sqrt.s";
+        D(opn = "sqrt.s");
         break;
     case OPC_ABS_S:
         {
@@ -6508,7 +6562,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "abs.s";
+        D(opn = "abs.s");
         break;
     case OPC_MOV_S:
         {
@@ -6518,7 +6572,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "mov.s";
+        D(opn = "mov.s");
         break;
     case OPC_NEG_S:
         {
@@ -6529,7 +6583,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "neg.s";
+        D(opn = "neg.s");
         break;
     case OPC_ROUND_L_S:
         check_cp1_64bitmode(ctx);
@@ -6543,7 +6597,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "round.l.s";
+        D(opn = "round.l.s");
         break;
     case OPC_TRUNC_L_S:
         check_cp1_64bitmode(ctx);
@@ -6557,7 +6611,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "trunc.l.s";
+        D(opn = "trunc.l.s");
         break;
     case OPC_CEIL_L_S:
         check_cp1_64bitmode(ctx);
@@ -6571,7 +6625,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "ceil.l.s";
+        D(opn = "ceil.l.s");
         break;
     case OPC_FLOOR_L_S:
         check_cp1_64bitmode(ctx);
@@ -6585,7 +6639,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "floor.l.s";
+        D(opn = "floor.l.s");
         break;
     case OPC_ROUND_W_S:
         {
@@ -6596,7 +6650,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "round.w.s";
+        D(opn = "round.w.s");
         break;
     case OPC_TRUNC_W_S:
         {
@@ -6607,7 +6661,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "trunc.w.s";
+        D(opn = "trunc.w.s");
         break;
     case OPC_CEIL_W_S:
         {
@@ -6618,7 +6672,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "ceil.w.s";
+        D(opn = "ceil.w.s");
         break;
     case OPC_FLOOR_W_S:
         {
@@ -6629,11 +6683,11 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "floor.w.s";
+        D(opn = "floor.w.s");
         break;
     case OPC_MOVCF_S:
         gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
-        opn = "movcf.s";
+        D(opn = "movcf.s");
         break;
     case OPC_MOVZ_S:
         {
@@ -6649,7 +6703,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i32(fp0);
             gen_set_label(l1);
         }
-        opn = "movz.s";
+        D(opn = "movz.s");
         break;
     case OPC_MOVN_S:
         {
@@ -6665,7 +6719,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
                 gen_set_label(l1);
             }
         }
-        opn = "movn.s";
+        D(opn = "movn.s");
         break;
     case OPC_RECIP_S:
         check_cop1x(ctx);
@@ -6677,7 +6731,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "recip.s";
+        D(opn = "recip.s");
         break;
     case OPC_RSQRT_S:
         check_cop1x(ctx);
@@ -6689,7 +6743,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "rsqrt.s";
+        D(opn = "rsqrt.s");
         break;
     case OPC_RECIP2_S:
         check_cp1_64bitmode(ctx);
@@ -6704,7 +6758,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "recip2.s";
+        D(opn = "recip2.s");
         break;
     case OPC_RECIP1_S:
         check_cp1_64bitmode(ctx);
@@ -6716,7 +6770,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "recip1.s";
+        D(opn = "recip1.s");
         break;
     case OPC_RSQRT1_S:
         check_cp1_64bitmode(ctx);
@@ -6728,7 +6782,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "rsqrt1.s";
+        D(opn = "rsqrt1.s");
         break;
     case OPC_RSQRT2_S:
         check_cp1_64bitmode(ctx);
@@ -6743,7 +6797,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "rsqrt2.s";
+        D(opn = "rsqrt2.s");
         break;
     case OPC_CVT_D_S:
         check_cp1_registers(ctx, fd);
@@ -6757,7 +6811,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "cvt.d.s";
+        D(opn = "cvt.d.s");
         break;
     case OPC_CVT_W_S:
         {
@@ -6768,7 +6822,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "cvt.w.s";
+        D(opn = "cvt.w.s");
         break;
     case OPC_CVT_L_S:
         check_cp1_64bitmode(ctx);
@@ -6782,7 +6836,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "cvt.l.s";
+        D(opn = "cvt.l.s");
         break;
     case OPC_CVT_PS_S:
         check_cp1_64bitmode(ctx);
@@ -6799,7 +6853,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "cvt.ps.s";
+        D(opn = "cvt.ps.s");
         break;
     case OPC_CMP_F_S:
     case OPC_CMP_UN_S:
@@ -6819,10 +6873,10 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
     case OPC_CMP_NGT_S:
         if (ctx->opcode & (1 << 6)) {
             gen_cmpabs_s(ctx, func-48, ft, fs, cc);
-            opn = condnames_abs[func-48];
+            D(opn = condnames_abs[func-48]);
         } else {
             gen_cmp_s(ctx, func-48, ft, fs, cc);
-            opn = condnames[func-48];
+            D(opn = condnames[func-48]);
         }
         break;
     case OPC_ADD_D:
@@ -6838,7 +6892,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "add.d";
+        D(opn = "add.d");
         optype = BINOP;
         break;
     case OPC_SUB_D:
@@ -6854,7 +6908,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "sub.d";
+        D(opn = "sub.d");
         optype = BINOP;
         break;
     case OPC_MUL_D:
@@ -6870,7 +6924,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "mul.d";
+        D(opn = "mul.d");
         optype = BINOP;
         break;
     case OPC_DIV_D:
@@ -6886,7 +6940,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "div.d";
+        D(opn = "div.d");
         optype = BINOP;
         break;
     case OPC_SQRT_D:
@@ -6899,7 +6953,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "sqrt.d";
+        D(opn = "sqrt.d");
         break;
     case OPC_ABS_D:
         check_cp1_registers(ctx, fs | fd);
@@ -6911,7 +6965,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "abs.d";
+        D(opn = "abs.d");
         break;
     case OPC_MOV_D:
         check_cp1_registers(ctx, fs | fd);
@@ -6922,7 +6976,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "mov.d";
+        D(opn = "mov.d");
         break;
     case OPC_NEG_D:
         check_cp1_registers(ctx, fs | fd);
@@ -6934,7 +6988,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "neg.d";
+        D(opn = "neg.d");
         break;
     case OPC_ROUND_L_D:
         check_cp1_64bitmode(ctx);
@@ -6946,7 +7000,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "round.l.d";
+        D(opn = "round.l.d");
         break;
     case OPC_TRUNC_L_D:
         check_cp1_64bitmode(ctx);
@@ -6958,7 +7012,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "trunc.l.d";
+        D(opn = "trunc.l.d");
         break;
     case OPC_CEIL_L_D:
         check_cp1_64bitmode(ctx);
@@ -6970,7 +7024,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "ceil.l.d";
+        D(opn = "ceil.l.d");
         break;
     case OPC_FLOOR_L_D:
         check_cp1_64bitmode(ctx);
@@ -6982,7 +7036,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "floor.l.d";
+        D(opn = "floor.l.d");
         break;
     case OPC_ROUND_W_D:
         check_cp1_registers(ctx, fs);
@@ -6996,7 +7050,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "round.w.d";
+        D(opn = "round.w.d");
         break;
     case OPC_TRUNC_W_D:
         check_cp1_registers(ctx, fs);
@@ -7010,7 +7064,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "trunc.w.d";
+        D(opn = "trunc.w.d");
         break;
     case OPC_CEIL_W_D:
         check_cp1_registers(ctx, fs);
@@ -7024,7 +7078,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "ceil.w.d";
+        D(opn = "ceil.w.d");
         break;
     case OPC_FLOOR_W_D:
         check_cp1_registers(ctx, fs);
@@ -7038,11 +7092,11 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "floor.w.d";
+        D(opn = "floor.w.d");
         break;
     case OPC_MOVCF_D:
         gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
-        opn = "movcf.d";
+        D(opn = "movcf.d");
         break;
     case OPC_MOVZ_D:
         {
@@ -7058,7 +7112,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i64(fp0);
             gen_set_label(l1);
         }
-        opn = "movz.d";
+        D(opn = "movz.d");
         break;
     case OPC_MOVN_D:
         {
@@ -7074,7 +7128,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
                 gen_set_label(l1);
             }
         }
-        opn = "movn.d";
+        D(opn = "movn.d");
         break;
     case OPC_RECIP_D:
         check_cp1_64bitmode(ctx);
@@ -7086,7 +7140,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "recip.d";
+        D(opn = "recip.d");
         break;
     case OPC_RSQRT_D:
         check_cp1_64bitmode(ctx);
@@ -7098,7 +7152,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "rsqrt.d";
+        D(opn = "rsqrt.d");
         break;
     case OPC_RECIP2_D:
         check_cp1_64bitmode(ctx);
@@ -7113,7 +7167,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "recip2.d";
+        D(opn = "recip2.d");
         break;
     case OPC_RECIP1_D:
         check_cp1_64bitmode(ctx);
@@ -7125,7 +7179,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "recip1.d";
+        D(opn = "recip1.d");
         break;
     case OPC_RSQRT1_D:
         check_cp1_64bitmode(ctx);
@@ -7137,7 +7191,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "rsqrt1.d";
+        D(opn = "rsqrt1.d");
         break;
     case OPC_RSQRT2_D:
         check_cp1_64bitmode(ctx);
@@ -7152,7 +7206,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "rsqrt2.d";
+        D(opn = "rsqrt2.d");
         break;
     case OPC_CMP_F_D:
     case OPC_CMP_UN_D:
@@ -7172,10 +7226,10 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
     case OPC_CMP_NGT_D:
         if (ctx->opcode & (1 << 6)) {
             gen_cmpabs_d(ctx, func-48, ft, fs, cc);
-            opn = condnames_abs[func-48];
+            D(opn = condnames_abs[func-48]);
         } else {
             gen_cmp_d(ctx, func-48, ft, fs, cc);
-            opn = condnames[func-48];
+            D(opn = condnames[func-48]);
         }
         break;
     case OPC_CVT_S_D:
@@ -7190,7 +7244,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "cvt.s.d";
+        D(opn = "cvt.s.d");
         break;
     case OPC_CVT_W_D:
         check_cp1_registers(ctx, fs);
@@ -7204,7 +7258,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "cvt.w.d";
+        D(opn = "cvt.w.d");
         break;
     case OPC_CVT_L_D:
         check_cp1_64bitmode(ctx);
@@ -7216,7 +7270,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "cvt.l.d";
+        D(opn = "cvt.l.d");
         break;
     case OPC_CVT_S_W:
         {
@@ -7227,7 +7281,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "cvt.s.w";
+        D(opn = "cvt.s.w");
         break;
     case OPC_CVT_D_W:
         check_cp1_registers(ctx, fd);
@@ -7241,7 +7295,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(fp64);
         }
-        opn = "cvt.d.w";
+        D(opn = "cvt.d.w");
         break;
     case OPC_CVT_S_L:
         check_cp1_64bitmode(ctx);
@@ -7255,7 +7309,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp32, fd);
             tcg_temp_free_i32(fp32);
         }
-        opn = "cvt.s.l";
+        D(opn = "cvt.s.l");
         break;
     case OPC_CVT_D_L:
         check_cp1_64bitmode(ctx);
@@ -7267,7 +7321,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "cvt.d.l";
+        D(opn = "cvt.d.l");
         break;
     case OPC_CVT_PS_PW:
         check_cp1_64bitmode(ctx);
@@ -7279,7 +7333,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "cvt.ps.pw";
+        D(opn = "cvt.ps.pw");
         break;
     case OPC_ADD_PS:
         check_cp1_64bitmode(ctx);
@@ -7294,7 +7348,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "add.ps";
+        D(opn = "add.ps");
         break;
     case OPC_SUB_PS:
         check_cp1_64bitmode(ctx);
@@ -7309,7 +7363,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "sub.ps";
+        D(opn = "sub.ps");
         break;
     case OPC_MUL_PS:
         check_cp1_64bitmode(ctx);
@@ -7324,7 +7378,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "mul.ps";
+        D(opn = "mul.ps");
         break;
     case OPC_ABS_PS:
         check_cp1_64bitmode(ctx);
@@ -7336,7 +7390,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "abs.ps";
+        D(opn = "abs.ps");
         break;
     case OPC_MOV_PS:
         check_cp1_64bitmode(ctx);
@@ -7347,7 +7401,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "mov.ps";
+        D(opn = "mov.ps");
         break;
     case OPC_NEG_PS:
         check_cp1_64bitmode(ctx);
@@ -7359,12 +7413,12 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "neg.ps";
+        D(opn = "neg.ps");
         break;
     case OPC_MOVCF_PS:
         check_cp1_64bitmode(ctx);
         gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
-        opn = "movcf.ps";
+        D(opn = "movcf.ps");
         break;
     case OPC_MOVZ_PS:
         check_cp1_64bitmode(ctx);
@@ -7380,7 +7434,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i64(fp0);
             gen_set_label(l1);
         }
-        opn = "movz.ps";
+        D(opn = "movz.ps");
         break;
     case OPC_MOVN_PS:
         check_cp1_64bitmode(ctx);
@@ -7397,7 +7451,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
                 gen_set_label(l1);
             }
         }
-        opn = "movn.ps";
+        D(opn = "movn.ps");
         break;
     case OPC_ADDR_PS:
         check_cp1_64bitmode(ctx);
@@ -7412,7 +7466,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "addr.ps";
+        D(opn = "addr.ps");
         break;
     case OPC_MULR_PS:
         check_cp1_64bitmode(ctx);
@@ -7427,7 +7481,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "mulr.ps";
+        D(opn = "mulr.ps");
         break;
     case OPC_RECIP2_PS:
         check_cp1_64bitmode(ctx);
@@ -7442,7 +7496,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "recip2.ps";
+        D(opn = "recip2.ps");
         break;
     case OPC_RECIP1_PS:
         check_cp1_64bitmode(ctx);
@@ -7454,7 +7508,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "recip1.ps";
+        D(opn = "recip1.ps");
         break;
     case OPC_RSQRT1_PS:
         check_cp1_64bitmode(ctx);
@@ -7466,7 +7520,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "rsqrt1.ps";
+        D(opn = "rsqrt1.ps");
         break;
     case OPC_RSQRT2_PS:
         check_cp1_64bitmode(ctx);
@@ -7481,7 +7535,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "rsqrt2.ps";
+        D(opn = "rsqrt2.ps");
         break;
     case OPC_CVT_S_PU:
         check_cp1_64bitmode(ctx);
@@ -7493,7 +7547,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "cvt.s.pu";
+        D(opn = "cvt.s.pu");
         break;
     case OPC_CVT_PW_PS:
         check_cp1_64bitmode(ctx);
@@ -7505,7 +7559,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "cvt.pw.ps";
+        D(opn = "cvt.pw.ps");
         break;
     case OPC_CVT_S_PL:
         check_cp1_64bitmode(ctx);
@@ -7517,7 +7571,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "cvt.s.pl";
+        D(opn = "cvt.s.pl");
         break;
     case OPC_PLL_PS:
         check_cp1_64bitmode(ctx);
@@ -7532,7 +7586,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i32(fp0);
             tcg_temp_free_i32(fp1);
         }
-        opn = "pll.ps";
+        D(opn = "pll.ps");
         break;
     case OPC_PLU_PS:
         check_cp1_64bitmode(ctx);
@@ -7547,7 +7601,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i32(fp0);
             tcg_temp_free_i32(fp1);
         }
-        opn = "plu.ps";
+        D(opn = "plu.ps");
         break;
     case OPC_PUL_PS:
         check_cp1_64bitmode(ctx);
@@ -7562,7 +7616,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i32(fp0);
             tcg_temp_free_i32(fp1);
         }
-        opn = "pul.ps";
+        D(opn = "pul.ps");
         break;
     case OPC_PUU_PS:
         check_cp1_64bitmode(ctx);
@@ -7577,7 +7631,7 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
             tcg_temp_free_i32(fp0);
             tcg_temp_free_i32(fp1);
         }
-        opn = "puu.ps";
+        D(opn = "puu.ps");
         break;
     case OPC_CMP_F_PS:
     case OPC_CMP_UN_PS:
@@ -7597,10 +7651,10 @@ static void gen_farith (DisasContext *ctx,
enum fopcode op1,
     case OPC_CMP_NGT_PS:
         if (ctx->opcode & (1 << 6)) {
             gen_cmpabs_ps(ctx, func-48, ft, fs, cc);
-            opn = condnames_abs[func-48];
+            D(opn = condnames_abs[func-48]);
         } else {
             gen_cmp_ps(ctx, func-48, ft, fs, cc);
-            opn = condnames[func-48];
+            D(opn = condnames[func-48]);
         }
         break;
     default:
@@ -7625,8 +7679,10 @@ static void gen_farith (DisasContext *ctx, enum
fopcode op1,
 static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
                            int fd, int fs, int base, int index)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "extended float load/store";
     int store = 0;
+#endif
     TCGv t0 = tcg_temp_new();

     if (base == 0) {
@@ -7651,7 +7707,7 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
-        opn = "lwxc1";
+        D(opn = "lwxc1");
         break;
     case OPC_LDXC1:
         check_cop1x(ctx);
@@ -7663,7 +7719,7 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "ldxc1";
+        D(opn = "ldxc1");
         break;
     case OPC_LUXC1:
         check_cp1_64bitmode(ctx);
@@ -7675,7 +7731,7 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(fp0);
         }
-        opn = "luxc1";
+        D(opn = "luxc1");
         break;
     case OPC_SWXC1:
         check_cop1x(ctx);
@@ -7689,8 +7745,8 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             tcg_temp_free_i32(fp0);
             tcg_temp_free(t1);
         }
-        opn = "swxc1";
-        store = 1;
+        D(opn = "swxc1");
+        D(store = 1);
         break;
     case OPC_SDXC1:
         check_cop1x(ctx);
@@ -7702,8 +7758,8 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
             tcg_temp_free_i64(fp0);
         }
-        opn = "sdxc1";
-        store = 1;
+        D(opn = "sdxc1");
+        D(store = 1);
         break;
     case OPC_SUXC1:
         check_cp1_64bitmode(ctx);
@@ -7715,8 +7771,8 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
             tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx);
             tcg_temp_free_i64(fp0);
         }
-        opn = "suxc1";
-        store = 1;
+        D(opn = "suxc1");
+        D(store = 1);
         break;
     }
     tcg_temp_free(t0);
@@ -7727,7 +7783,9 @@ static void gen_flt3_ldst (DisasContext *ctx,
uint32_t opc,
 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
                             int fd, int fr, int fs, int ft)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "flt3_arith";
+#endif

     switch (opc) {
     case OPC_ALNV_PS:
@@ -7766,7 +7824,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             tcg_temp_free_i32(fp);
             tcg_temp_free_i32(fph);
         }
-        opn = "alnv.ps";
+        D(opn = "alnv.ps");
         break;
     case OPC_MADD_S:
         check_cop1x(ctx);
@@ -7784,7 +7842,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr32(fp2, fd);
             tcg_temp_free_i32(fp2);
         }
-        opn = "madd.s";
+        D(opn = "madd.s");
         break;
     case OPC_MADD_D:
         check_cop1x(ctx);
@@ -7803,7 +7861,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "madd.d";
+        D(opn = "madd.d");
         break;
     case OPC_MADD_PS:
         check_cp1_64bitmode(ctx);
@@ -7821,7 +7879,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "madd.ps";
+        D(opn = "madd.ps");
         break;
     case OPC_MSUB_S:
         check_cop1x(ctx);
@@ -7839,7 +7897,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr32(fp2, fd);
             tcg_temp_free_i32(fp2);
         }
-        opn = "msub.s";
+        D(opn = "msub.s");
         break;
     case OPC_MSUB_D:
         check_cop1x(ctx);
@@ -7858,7 +7916,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "msub.d";
+        D(opn = "msub.d");
         break;
     case OPC_MSUB_PS:
         check_cp1_64bitmode(ctx);
@@ -7876,7 +7934,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "msub.ps";
+        D(opn = "msub.ps");
         break;
     case OPC_NMADD_S:
         check_cop1x(ctx);
@@ -7894,7 +7952,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr32(fp2, fd);
             tcg_temp_free_i32(fp2);
         }
-        opn = "nmadd.s";
+        D(opn = "nmadd.s");
         break;
     case OPC_NMADD_D:
         check_cop1x(ctx);
@@ -7913,7 +7971,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "nmadd.d";
+        D(opn = "nmadd.d");
         break;
     case OPC_NMADD_PS:
         check_cp1_64bitmode(ctx);
@@ -7931,7 +7989,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "nmadd.ps";
+        D(opn = "nmadd.ps");
         break;
     case OPC_NMSUB_S:
         check_cop1x(ctx);
@@ -7949,7 +8007,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr32(fp2, fd);
             tcg_temp_free_i32(fp2);
         }
-        opn = "nmsub.s";
+        D(opn = "nmsub.s");
         break;
     case OPC_NMSUB_D:
         check_cop1x(ctx);
@@ -7968,7 +8026,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "nmsub.d";
+        D(opn = "nmsub.d");
         break;
     case OPC_NMSUB_PS:
         check_cp1_64bitmode(ctx);
@@ -7986,7 +8044,7 @@ static void gen_flt3_arith (DisasContext *ctx,
uint32_t opc,
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(fp2);
         }
-        opn = "nmsub.ps";
+        D(opn = "nmsub.ps");
         break;
     default:
         MIPS_INVAL(opn);
@@ -9914,7 +9972,9 @@ static void gen_ldxs (DisasContext *ctx, int
base, int index, int rd)
 static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
                            int base, int16_t offset)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "ldst_pair";
+#endif
     TCGv t0, t1;

     if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) {
@@ -9936,7 +9996,7 @@ static void gen_ldst_pair (DisasContext *ctx,
uint32_t opc, int rd,
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_lw(t1, t0, ctx);
         gen_store_gpr(t1, rd+1);
-        opn = "lwp";
+        D(opn = "lwp");
         break;
     case SWP:
         save_cpu_state(ctx, 1);
@@ -9946,7 +10006,7 @@ static void gen_ldst_pair (DisasContext *ctx,
uint32_t opc, int rd,
         gen_op_addr_add(ctx, t0, t0, t1);
         gen_load_gpr(t1, rd+1);
         op_st_sw(t1, t0, ctx);
-        opn = "swp";
+        D(opn = "swp");
         break;
 #ifdef TARGET_MIPS64
     case LDP:
@@ -9957,7 +10017,7 @@ static void gen_ldst_pair (DisasContext *ctx,
uint32_t opc, int rd,
         gen_op_addr_add(ctx, t0, t0, t1);
         op_ld_ld(t1, t0, ctx);
         gen_store_gpr(t1, rd+1);
-        opn = "ldp";
+        D(opn = "ldp");
         break;
     case SDP:
         save_cpu_state(ctx, 1);
@@ -9967,7 +10027,7 @@ static void gen_ldst_pair (DisasContext *ctx,
uint32_t opc, int rd,
         gen_op_addr_add(ctx, t0, t0, t1);
         gen_load_gpr(t1, rd+1);
         op_st_sd(t1, t0, ctx);
-        opn = "sdp";
+        D(opn = "sdp");
         break;
 #endif
     }
Paolo Bonzini - Oct. 7, 2010, 7:29 a.m.
On 10/06/2010 11:34 PM, Blue Swirl wrote:
> Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
> /src/qemu/target-mips/translate.c: In function 'gen_ld':
> /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set
> but not used [-Werror=unused-but-set-variable]
>
> Fix by making the variable declarations and uses conditional to debugging.

What about a set_opn macro instead of this one-off "D" idiom?

Paolo
Markus Armbruster - Oct. 7, 2010, 12:35 p.m.
Paolo Bonzini <pbonzini@redhat.com> writes:

> On 10/06/2010 11:34 PM, Blue Swirl wrote:
>> Compiling with GCC 4.6.0 20100925 produced a lot of warnings like:
>> /src/qemu/target-mips/translate.c: In function 'gen_ld':
>> /src/qemu/target-mips/translate.c:1039:17: error: variable 'opn' set
>> but not used [-Werror=unused-but-set-variable]
>>
>> Fix by making the variable declarations and uses conditional to debugging.
>
> What about a set_opn macro instead of this one-off "D" idiom?

Even simpler: a few judiciously placed (void)opn.

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 20b66a8..3389013 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -562,9 +562,11 @@  static const char *fregnames[] =
                        TARGET_FMT_lx ": %08x " fmt "\n", \
                        ctx->pc, ctx->opcode , ## __VA_ARGS__)
 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
+#define D(x) x
 #else
 #define MIPS_DEBUG(fmt, ...) do { } while(0)
 #define LOG_DISAS(...) do { } while (0)
+#define D(x) do { } while (0)
 #endif

 #define MIPS_INVAL(op)                                                        \
@@ -1036,7 +1038,9 @@  static target_ulong pc_relative_pc (DisasContext *ctx)
 static void gen_ld (CPUState *env, DisasContext *ctx, uint32_t opc,
                     int rt, int base, int16_t offset)
 {
+#ifdef MIPS_DEBUG_DISAS
     const char *opn = "ld";
+#endif
     TCGv t0, t1;

     if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) {
@@ -1057,33 +1061,33 @@  static void gen_ld (CPUState *env,
DisasContext *ctx, uint32_t opc,
         save_cpu_state(ctx, 0);
         op_ld_lwu(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lwu";
+        D(opn = "lwu");
         break;
     case OPC_LD:
         save_cpu_state(ctx, 0);
         op_ld_ld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "ld";
+        D(opn = "ld");
         break;
     case OPC_LLD:
         save_cpu_state(ctx, 0);
         op_ld_lld(t0, t0, ctx);
         gen_store_gpr(t0, rt);
-        opn = "lld";
+        D(opn = "lld");
         break;
     case OPC_LDL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
         gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
-        opn = "ldl";
+        D(opn = "ldl");
         break;
     case OPC_LDR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(t1, rt);
         gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
-        opn = "ldr";
+        D(opn = "ldr");
         break;
     case OPC_LDPC: