From patchwork Wed Oct  6 09:25:29 2010
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Subject: fix bootstrap on !altivec powerpc configurations
Date: Tue, 05 Oct 2010 23:25:29 -0000
From: Olivier Hainque <hainque@adacore.com>
X-Patchwork-Id: 66900
Message-Id: <20101006092529.GA28471@cardhu.act-europe.fr>
To: gcc-patches@gcc.gnu.org
Cc: hainque@adacore.com

Hello,

Since a series of changes introduced from
 http://gcc.gnu.org/ml/gcc-patches/2009-07/txt00039.txt

bootstrap is broken for powerpc targets missing altivec support. We
noticed trying to build for aix 5.2.

The failure comes from errors compiling rs6000_expand_ternop_builtin:

  if (icode == CODE_FOR_nothing)
    /* Builtin not supported on this processor.  */
    return 0;
  ...
  switch (icode)
    {
    case CODE_FOR_altivec_vsldoi_v4sf:
    case CODE_FOR_altivec_vsldoi_v4si:
    case CODE_FOR_altivec_vsldoi_v8hi:
  ...

where the switch statement has multiple "CODE_FOR_nothing" alternatives.

The attached patch fixes this by rewriting the switch as a sequence of
'if's. This fixed our build on aix 5.2, and was bootstrapped + reg tested
on aix 5.3.

OK ?

Thanks in avdance,

2010-10-06  Olivier Hainque  <hainque@adacore.com>

	* config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Rewrite
	switch on insn codes as sequence of ifs.


--- config/rs6000/rs6000.c	(revision 163943)
+++ config/rs6000/rs6000.c	(working copy)
@@ -10830,12 +10830,18 @@ rs6000_expand_ternop_builtin
       || arg2 == error_mark_node)
     return const0_rtx;
 
-  switch (icode)
+  /* Check and prepare argument depending on the instruction code.
+
+     Note that a switch statement instead of the sequence of tests
+     would be incorrect as many of the CODE_FOR values could be
+     CODE_FOR_nothing and that would yield multiple alternatives
+     with identical values.  We'd never reach here at runtime in
+     this case.  */
+  if (icode == CODE_FOR_altivec_vsldoi_v4sf
+      || icode == CODE_FOR_altivec_vsldoi_v4si
+      || icode == CODE_FOR_altivec_vsldoi_v8hi
+      || icode == CODE_FOR_altivec_vsldoi_v16qi)
     {
-    case CODE_FOR_altivec_vsldoi_v4sf:
-    case CODE_FOR_altivec_vsldoi_v4si:
-    case CODE_FOR_altivec_vsldoi_v8hi:
-    case CODE_FOR_altivec_vsldoi_v16qi:
       /* Only allow 4-bit unsigned literals.  */
       STRIP_NOPS (arg2);
       if (TREE_CODE (arg2) != INTEGER_CST
@@ -10844,16 +10850,16 @@
 	  error ("argument 3 must be a 4-bit unsigned literal");
 	  return const0_rtx;
 	}
-      break;
-
-    case CODE_FOR_vsx_xxpermdi_v2df:
-    case CODE_FOR_vsx_xxpermdi_v2di:
-    case CODE_FOR_vsx_xxsldwi_v16qi:
-    case CODE_FOR_vsx_xxsldwi_v8hi:
-    case CODE_FOR_vsx_xxsldwi_v4si:
-    case CODE_FOR_vsx_xxsldwi_v4sf:
-    case CODE_FOR_vsx_xxsldwi_v2di:
-    case CODE_FOR_vsx_xxsldwi_v2df:
+    }
+  else if (icode == CODE_FOR_vsx_xxpermdi_v2df
+           || icode == CODE_FOR_vsx_xxpermdi_v2di
+           || icode == CODE_FOR_vsx_xxsldwi_v16qi
+           || icode == CODE_FOR_vsx_xxsldwi_v8hi
+           || icode == CODE_FOR_vsx_xxsldwi_v4si
+           || icode == CODE_FOR_vsx_xxsldwi_v4sf
+           || icode == CODE_FOR_vsx_xxsldwi_v2di
+           || icode == CODE_FOR_vsx_xxsldwi_v2df)
+    {
       /* Only allow 2-bit unsigned literals.  */
       STRIP_NOPS (arg2);
       if (TREE_CODE (arg2) != INTEGER_CST
@@ -10862,10 +10868,10 @@
 	  error ("argument 3 must be a 2-bit unsigned literal");
 	  return const0_rtx;
 	}
-      break;
-
-    case CODE_FOR_vsx_set_v2df:
-    case CODE_FOR_vsx_set_v2di:
+    }
+  else if (icode == CODE_FOR_vsx_set_v2df
+           || icode == CODE_FOR_vsx_set_v2di)
+    {
       /* Only allow 1-bit unsigned literals.  */
       STRIP_NOPS (arg2);
       if (TREE_CODE (arg2) != INTEGER_CST
@@ -10874,10 +10880,6 @@
 	  error ("argument 3 must be a 1-bit unsigned literal");
 	  return const0_rtx;
 	}
-      break;
-
-    default:
-      break;
     }
 
   if (target == 0