| Message ID | 20160909134412.24643-7-paul.burton@imgtec.com |
|---|---|
| State | Superseded |
| Delegated to: | Daniel Schwierzeck |
| Headers | show |
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6aec430..6f1d219 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -142,15 +142,24 @@ reset: PTR_L gp, 0(ra) #ifndef CONFIG_SKIP_LOWLEVEL_INIT +# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD /* Initialize any external memory */ PTR_LA t9, lowlevel_init jalr t9 nop +# endif /* Initialize caches... */ PTR_LA t9, mips_cache_reset jalr t9 nop + +# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* Initialize any external memory */ + PTR_LA t9, lowlevel_init + jalr t9 + nop +# endif #endif /* Set up temporary stack */
On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com> --- Changes in v2: None arch/mips/cpu/start.S | 9 +++++++++ 1 file changed, 9 insertions(+)