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[RFC,v1,11/29] target-arc: BCLR, BMSK, BSET, BTST, BXOR

Message ID 1473373930-31547-12-git-send-email-mrolnik@gmail.com
State New
Headers show

Commit Message

Michael Rolnik Sept. 8, 2016, 10:31 p.m. UTC 
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
---
 target-arc/translate-inst.c | 139 ++++++++++++++++++++++++++++++++++++++++++++
 target-arc/translate-inst.h |   6 ++
 2 files changed, 145 insertions(+)

Comments

Richard Henderson Sept. 21, 2016, 12:07 a.m. UTC | #1 
On 09/08/2016 03:31 PM, Michael Rolnik wrote:
> +int arc_gen_BCLR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
> +{
> +    TCGv rslt = dest;
> +
> +    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
> +        rslt = tcg_temp_new_i32();
> +    }
> +
> +    tcg_gen_andi_tl(rslt, src2, 0x3f);

0x1f, in all of the functions.

> +    tcg_gen_add_tl(mask, mask, ctx->one);
> +    tcg_gen_shr_tl(mask, ctx->one, mask);
> +    tcg_gen_sub_tl(mask, mask, ctx->one);

I know this is the description in the manual, but this will produce a shift of 
32 with an input of 31, which is illegal in tcg.

You need to use

   mask = -1u >> (src2 ^ 31)


r~
diff mbox

Patch

diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 2a579f8..91b7037 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -1169,3 +1169,142 @@  int arc_gen_PUSH(DisasCtxt *ctx, TCGv src1)
     return BS_NONE;
 }
 
+/*
+    BCLR
+*/
+int arc_gen_BCLR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_andi_tl(rslt, src2, 0x3f);
+    tcg_gen_shr_tl(rslt, ctx->one, rslt);
+    tcg_gen_andc_tl(rslt, src1, rslt);  /*  rslt = src1 & ~(1 << src2)      */
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    BMSK
+*/
+int arc_gen_BMSK(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+    TCGv mask = tcg_temp_new_i32();
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_andi_tl(mask, src2, 0x3f);
+    tcg_gen_add_tl(mask, mask, ctx->one);
+    tcg_gen_shr_tl(mask, ctx->one, mask);
+    tcg_gen_sub_tl(mask, mask, ctx->one);
+
+    tcg_gen_and_tl(rslt, src1, mask);
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    tcg_temp_free_i32(mask);
+
+    return  BS_NONE;
+}
+
+/*
+    BSET
+*/
+int arc_gen_BSET(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_andi_tl(rslt, src2, 0x3f);
+    tcg_gen_shr_tl(rslt, ctx->one, rslt);
+    tcg_gen_or_tl(rslt, src1, rslt);    /*  rslt = src1 | (1 << src2)   */
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
+/*
+    BTST
+*/
+int arc_gen_BTST(DisasCtxt *ctx, TCGv src1, TCGv src2)
+{
+    TCGv rslt = tcg_temp_new_i32();
+
+    tcg_gen_andi_tl(rslt, src2, 0x3f);
+    tcg_gen_shr_tl(rslt, ctx->one, rslt);
+    tcg_gen_and_tl(rslt, src1, rslt);       /*  rslt = src1 & (1 << src2)   */
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    tcg_temp_free_i32(rslt);
+
+    return  BS_NONE;
+}
+
+/*
+    BXOR
+*/
+int arc_gen_BXOR(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+    TCGv rslt = dest;
+
+    if (TCGV_EQUAL(dest, src1) || TCGV_EQUAL(dest, src2)) {
+        rslt = tcg_temp_new_i32();
+    }
+
+    tcg_gen_andi_tl(rslt, src2, 0x3f);
+    tcg_gen_shr_tl(rslt, ctx->one, rslt);
+    tcg_gen_xor_tl(rslt, src1, rslt);       /*  rslt = src1 ^ (1 << src2)   */
+
+    if (ctx->opt.f) {
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+        tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+    }
+
+    if (!TCGV_EQUAL(dest, rslt)) {
+        tcg_gen_mov_tl(dest, rslt);
+        tcg_temp_free_i32(rslt);
+    }
+
+    return  BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index d088a43..88cae1c 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -78,3 +78,9 @@  int arc_gen_NOT(DisasCtxt *c, TCGv dest, TCGv src1);
 int arc_gen_POP(DisasCtxt *c, TCGv src1);
 int arc_gen_PUSH(DisasCtxt *c, TCGv src1);
 
+int arc_gen_BCLR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_BMSK(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_BSET(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_BTST(DisasCtxt *c, TCGv src1, TCGv src2);
+int arc_gen_BXOR(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+