| Message ID | 1473354920-23906-1-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
On 09/08/2016 10:15 AM, Richard Henderson wrote: > Three unrelated patches and Pranith's memory barrier patch sets. > > The alignment patch is in support of Sparc's ldf instructions: > 8 and 16-byte memory operations that require only 4-byte alignment. > It's just as easy to support this kind of misalignment as any other. > As mentioned in the commit, we'd also forgotten to properly handle > arm32, mips, ia64 and sparc when it came to overalignment. > > I have a follow up patch set to make use of this for target-sparc. > > I've tweaked the memory barrier patch set. For aarch64, ppc > and sparc, I've fixed the insn selection a bit. I merged the > optimization pass into the current optimization pass. Ho hum. I think I've mucked something up here too. Please ignore this pull. r~
On Thu, Sep 8, 2016 at 4:38 PM, Richard Henderson <rth@twiddle.net> wrote: > On 09/08/2016 10:15 AM, Richard Henderson wrote: >> >> Three unrelated patches and Pranith's memory barrier patch sets. >> >> The alignment patch is in support of Sparc's ldf instructions: >> 8 and 16-byte memory operations that require only 4-byte alignment. >> It's just as easy to support this kind of misalignment as any other. >> As mentioned in the commit, we'd also forgotten to properly handle >> arm32, mips, ia64 and sparc when it came to overalignment. >> >> I have a follow up patch set to make use of this for target-sparc. >> >> I've tweaked the memory barrier patch set. For aarch64, ppc >> and sparc, I've fixed the insn selection a bit. I merged the >> optimization pass into the current optimization pass. > > > Ho hum. I think I've mucked something up here too. > Please ignore this pull. > I think I found the error. It looks like the fence optimization patch is causing the error. I will reply in that patch. -- Pranith
On Thu, Sep 8, 2016 at 7:49 PM, Pranith Kumar <bobby.prani+qemu@gmail.com> wrote: >> On 09/08/2016 10:15 AM, Richard Henderson wrote: >> Ho hum. I think I've mucked something up here too. >> Please ignore this pull. >> > > I think I found the error. It looks like the fence optimization patch > is causing the error. > > I will reply in that patch. > Hmmm, looking closer, the optimization patch looks fine. What error are you seeing? -- Pranith
On 09/08/2016 05:06 PM, Pranith Kumar wrote:
> What error are you seeing?
Something else entirely.
My alpha kernel is crashing. I thought it was something in this patch set,
after I rebased, but now I can see it's in HEAD too. I'll have to spend some
time tracking it down.
r~
On 09/08/2016 11:51 PM, Richard Henderson wrote: > On 09/08/2016 05:06 PM, Pranith Kumar wrote: >> What error are you seeing? > > Something else entirely. > > My alpha kernel is crashing. I thought it was something in this patch set, > after I rebased, but now I can see it's in HEAD too. I'll have to spend some > time tracking it down. Well, the best I can figure, we've got a missing dependency in the makefiles somewhere. Which, does explain the segv backtrace that made no sense. I can't imagine what is wrong with the makefile, seeing as I used "make clean" from time to time in order to drop optimization from cflags. But I built quite a lot of git versions, all of which failed until I deleted the build directory. After that, everything works. Ho hum. I'll set up another pull request. r~
Three unrelated patches and Pranith's memory barrier patch sets. The alignment patch is in support of Sparc's ldf instructions: 8 and 16-byte memory operations that require only 4-byte alignment. It's just as easy to support this kind of misalignment as any other. As mentioned in the commit, we'd also forgotten to properly handle arm32, mips, ia64 and sparc when it came to overalignment. I have a follow up patch set to make use of this for target-sparc. I've tweaked the memory barrier patch set. For aarch64, ppc and sparc, I've fixed the insn selection a bit. I merged the optimization pass into the current optimization pass. r~ [v2: With actual pull data this time, cover letter only.] The following changes since commit 2926375cffce464fde6b4dabaed1e133d549af39: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-09-06 17:18:17 +0100) are available in the git repository at: git://github.com/rth7680/qemu.git tags/pull-tcg-20160908 for you to fetch changes up to a36ae2f6ad489d510ada40bf2aab9539e4a97511: tcg: Optimize fence instructions (2016-09-07 13:46:01 -0700) ---------------------------------------------------------------- Alignment, memory barrier, and misc patches. ---------------------------------------------------------------- Pranith Kumar (15): Introduce TCGOpcode for memory barrier tcg/i386: Add support for fence tcg/aarch64: Add support for fence tcg/arm: Add support for fence tcg/ia64: Add support for fence tcg/mips: Add support for fence tcg/ppc: Add support for fence tcg/s390: Add support for fence tcg/sparc: Add support for fence tcg/tci: Add support for fence target-arm: Generate fences in ARMv7 frontend target-alpha: Generate fence op target-aarch64: Generate fences for aarch64 target-i386: Generate fences for x86 tcg: Optimize fence instructions Richard Henderson (3): tcg: Support arbitrary size + alignment tcg: Merge GETPC and GETRA cpu-exec: Check -dfilter for -d cpu cpu-exec.c | 3 +- cputlb.c | 6 ++-- include/exec/exec-all.h | 9 ++--- softmmu_template.h | 48 ++++++++------------------ target-alpha/translate.c | 4 +-- target-arm/helper.c | 6 ++-- target-arm/translate-a64.c | 14 +++++++- target-arm/translate.c | 4 +-- target-i386/translate.c | 8 +++++ target-mips/op_helper.c | 18 +++++----- tcg/README | 17 ++++++++++ tcg/aarch64/tcg-target.inc.c | 35 +++++++++++++++---- tcg/arm/tcg-target.inc.c | 37 ++++++++++++++++---- tcg/i386/tcg-target.inc.c | 33 +++++++++++++----- tcg/ia64/tcg-target.inc.c | 27 +++++++++++---- tcg/mips/tcg-target.inc.c | 18 ++++++++-- tcg/optimize.c | 54 +++++++++++++++++++++++++++++ tcg/ppc/tcg-target.inc.c | 78 +++++++++++++++++++++++++++--------------- tcg/s390/tcg-target.inc.c | 24 ++++++++----- tcg/sparc/tcg-target.inc.c | 30 ++++++++++++---- tcg/tcg-op.c | 17 ++++++++++ tcg/tcg-op.h | 2 ++ tcg/tcg-opc.h | 2 ++ tcg/tcg.h | 81 +++++++++++++++++++++++++++----------------- tcg/tci/tcg-target.inc.c | 3 ++ tci.c | 4 +++ translate-all.c | 1 + user-exec.c | 7 ++-- 28 files changed, 421 insertions(+), 169 deletions(-)