From patchwork Sun Oct 3 13:07:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 66598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D9BBAB70D2 for ; Mon, 4 Oct 2010 00:07:38 +1100 (EST) Received: (qmail 20423 invoked by alias); 3 Oct 2010 13:07:35 -0000 Received: (qmail 20411 invoked by uid 22791); 3 Oct 2010 13:07:34 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 03 Oct 2010 13:07:28 +0000 Received: by qwb7 with SMTP id 7so2589527qwb.20 for ; Sun, 03 Oct 2010 06:07:26 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.66.27 with SMTP id l27mr5840990qai.41.1286111246381; Sun, 03 Oct 2010 06:07:26 -0700 (PDT) Received: by 10.229.84.4 with HTTP; Sun, 3 Oct 2010 06:07:26 -0700 (PDT) Date: Sun, 3 Oct 2010 15:07:26 +0200 Message-ID: Subject: [PATCH, i386]: Improve _mask splitters From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! Attached patch gives combine pass some more freedom when creating shifts with implicit count mask. 2010-10-03 Uros Bizjak * config/i386/i386.md (*ashl3_mask): Change operand 2 preticate to nonimmediate_operand. Force operand 2 to register when allowed. (*3_mask): Ditto. (*3_mask): Ditto. Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline. Uros. Index: i386.md =================================================================== --- i386.md (revision 164905) +++ i386.md (working copy) @@ -9152,14 +9152,13 @@ }) ;; Avoid useless masking of count operand. - (define_insn_and_split "*ashl3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 2 "nonimmediate_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, mode, operands) @@ -9170,7 +9169,12 @@ [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} [(set_attr "type" "ishift") (set_attr "mode" "")]) @@ -9714,14 +9718,13 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. - (define_insn_and_split "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 2 "nonimmediate_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) @@ -9732,7 +9735,12 @@ [(parallel [(set (match_dup 0) (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} [(set_attr "type" "ishift") (set_attr "mode" "")]) @@ -10089,14 +10097,13 @@ "ix86_expand_binary_operator (, mode, operands); DONE;") ;; Avoid useless masking of count operand. - (define_insn_and_split "*3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (any_rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI - (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 2 "nonimmediate_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands) @@ -10107,7 +10114,12 @@ [(parallel [(set (match_dup 0) (any_rotate:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" +{ + if (can_create_pseudo_p ()) + operands [2] = force_reg (SImode, operands[2]); + + operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0); +} [(set_attr "type" "rotate") (set_attr "mode" "")])