From patchwork Sat Oct 2 05:38:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Clark X-Patchwork-Id: 66556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D90EFB70D6 for ; Sat, 2 Oct 2010 15:50:24 +1000 (EST) Received: from localhost ([127.0.0.1]:53970 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P1uuW-0005zY-M3 for incoming@patchwork.ozlabs.org; Sat, 02 Oct 2010 01:45:28 -0400 Received: from [140.186.70.92] (port=41915 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P1ush-0005fb-Qi for qemu-devel@nongnu.org; Sat, 02 Oct 2010 01:43:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P1usg-0006EW-G6 for qemu-devel@nongnu.org; Sat, 02 Oct 2010 01:43:35 -0400 Received: from aibo.runbox.com ([87.238.52.70]:51518) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P1usg-0006E7-3I for qemu-devel@nongnu.org; Sat, 02 Oct 2010 01:43:34 -0400 Received: from [10.9.9.162] (helo=pepper.runbox.com) by greyhound.runbox.com with esmtp (Exim 4.50) id 1P1usd-0002kh-AV for qemu-devel@nongnu.org; Sat, 02 Oct 2010 07:43:31 +0200 Received: from cpe-72-228-136-88.buffalo.res.rr.com ([72.228.136.88] helo=[192.168.123.197]) by pepper.runbox.com with esmtpsa (uid:230665 ) (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.50) id 1P1unc-00054L-5e; Sat, 02 Oct 2010 07:38:20 +0200 Message-ID: <4CA6C549.9090801@runbox.com> Date: Sat, 02 Oct 2010 01:38:17 -0400 From: John Clark User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.12) Gecko/20100915 Thunderbird/3.0.8 MIME-Version: 1.0 To: qemu-devel@nongnu.org X-Enigmail-Version: 1.0.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 1) Subject: [Qemu-devel] Minor MMU fixes for PowerPC 40x emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hello, I found I had to make a few minor changes to the MMU code for the PowerPC 40x emulation to get NetBSD to run on a virtual PowerPC 405 core with qemu-system-ppcemb. The 'tlbre' instruction was not working, and permission checking for a TLB entry was not as strict as it should be. Diffs are included below. Thank you. - John Clark diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 3bc8a34..a8c1802 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1172,9 +1172,9 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, case 0x1: check_perms: /* Check from TLB entry */ - /* XXX: there is a problem here or in the TLB fill code... */ + /* There is no longer a need to force PAGE_EXEC permission here */ + /* because of the tlb->attr fix in helper_4xx_tlbwe_lo() */ ctx->prot = tlb->prot; - ctx->prot |= PAGE_EXEC; ret = check_prot(ctx->prot, rw, access_type); if (ret == -2) env->spr[SPR_40x_ESR] = 0; diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c index 3e6db85..54356e8 100644 --- a/target-ppc/op_helper.c +++ b/target-ppc/op_helper.c @@ -3929,7 +3929,7 @@ static inline int booke_page_size_to_tlb(target_ulong page_size) } /* Helpers for 4xx TLB management */ -target_ulong helper_4xx_tlbre_lo (target_ulong entry) +target_ulong helper_4xx_tlbre_hi (target_ulong entry) { ppcemb_tlb_t *tlb; target_ulong ret; @@ -3939,7 +3939,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry) tlb = &env->tlb[entry].tlbe; ret = tlb->EPN; if (tlb->prot & PAGE_VALID) - ret |= 0x400; + ret |= 0x40; /* V bit is 0x40, not 0x400 */ size = booke_page_size_to_tlb(tlb->size); if (size < 0 || size > 0x7) size = 1; @@ -3948,7 +3948,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry) return ret; } -target_ulong helper_4xx_tlbre_hi (target_ulong entry) +target_ulong helper_4xx_tlbre_lo (target_ulong entry) { ppcemb_tlb_t *tlb; target_ulong ret;