From patchwork Fri Oct 1 21:30:12 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 66522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 343F9B7122 for ; Sat, 2 Oct 2010 07:30:34 +1000 (EST) Received: (qmail 11264 invoked by alias); 1 Oct 2010 21:30:31 -0000 Received: (qmail 11250 invoked by uid 22791); 1 Oct 2010 21:30:29 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, TW_ZJ, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 01 Oct 2010 21:30:23 +0000 Received: by qwb7 with SMTP id 7so1802674qwb.20 for ; Fri, 01 Oct 2010 14:30:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.101.197 with SMTP id d5mr4339884qco.220.1285968620239; Fri, 01 Oct 2010 14:30:20 -0700 (PDT) Received: by 10.229.84.4 with HTTP; Fri, 1 Oct 2010 14:30:12 -0700 (PDT) Date: Fri, 1 Oct 2010 23:30:12 +0200 Message-ID: Subject: [PATCH, i386]: Truncate shift count From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! SHIFT_COUNT_TRUNCATED can't be used on i386 (see comment in gccint.info) and TARGET_SHIFT_TRUNCATION mask is not effective for some reason on attached testcase. To remove unnecessary and instructions on shift count, let's implement approach, proposed in the documentation: However, on some machines, such as the 80386 and the 680x0, truncation only applies to shift operations and not the (real or pretended) bit-field operations. Define `SHIFT_COUNT_TRUNCATED' to be zero on such machines. Instead, add patterns to the `md' file that include the implied truncation of the shift instructions. So, we add: (define_insn_and_split "*ashl3_mask" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0") (subreg:QI (and:SI (match_operand:SI 2 "register_operand" "c") (match_operand:SI 3 "const_int_operand" "n")) 0))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (ASHIFT, mode, operands) && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) == GET_MODE_BITSIZE (mode)-1" "#" "&& 1" [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" [(set_attr "type" "ishift") (set_attr "mode" "")]) And similar patterns for other shifts/rotates. The above pattern is effective for both, SImode and DImode shifts, since for both modes, combine always generate QImode subregs of SImode ANDs. I didn't manage to generate a HImode or QImode shift, the shift has always been promoted to SImode, so I have left them out. Also note, that ..._cmp version of the shift (that also sets flag register) operates only with constant shift arguments [see comments in i386.md about flags and shift-by-zero functionality], so this new pattern (that operates with variable shift argument exclusively) can't interfere with ..._cmp versions in any way. 2010-10-01 Uros Bizjak * config/i386/i386.md (*ashl3_mask): New insn_and_split pattern. (*3_mask): Ditto. (*3_mask): Ditto. testsuite/ChangeLog: 2010-10-01 Uros Bizjak * gcc.target/i386/shift_mask.c: New test. Patch was regression tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 164890) +++ config/i386/i386.md (working copy) @@ -9151,6 +9151,29 @@ DONE; }) +;; Avoid useless masking of count operand. + +(define_insn_and_split "*ashl3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (ashift:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (ASHIFT, mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (ashift:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" + [(set_attr "type" "ishift") + (set_attr "mode" "")]) + (define_insn "*ashl3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r") (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "0,l") @@ -9690,6 +9713,29 @@ "" "ix86_expand_binary_operator (, mode, operands); DONE;") +;; Avoid useless masking of count operand. + +(define_insn_and_split "*3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (any_shiftrt:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (any_shiftrt:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" + [(set_attr "type" "ishift") + (set_attr "mode" "")]) + (define_insn_and_split "*3_doubleword" [(set (match_operand:DWI 0 "register_operand" "=r") (any_shiftrt:DWI (match_operand:DWI 1 "register_operand" "0") @@ -10042,6 +10088,29 @@ "" "ix86_expand_binary_operator (, mode, operands); DONE;") +;; Avoid useless masking of count operand. + +(define_insn_and_split "*3_mask" + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") + (any_rotate:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "0") + (subreg:QI + (and:SI + (match_operand:SI 2 "register_operand" "c") + (match_operand:SI 3 "const_int_operand" "n")) 0))) + (clobber (reg:CC FLAGS_REG))] + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + == GET_MODE_BITSIZE (mode)-1" + "#" + "&& 1" + [(parallel [(set (match_dup 0) + (any_rotate:SWI48 (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "operands[2] = simplify_gen_subreg (QImode, operands[2], SImode, 0);" + [(set_attr "type" "rotate") + (set_attr "mode" "")]) + ;; Implement rotation using two double-precision ;; shift instructions and a scratch register. Index: testsuite/gcc.target/i386/shift_mask.c =================================================================== --- testsuite/gcc.target/i386/shift_mask.c (revision 0) +++ testsuite/gcc.target/i386/shift_mask.c (revision 0) @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int test_sal (int a, int c) +{ + return a << (c & 0x1f); +} + +int test_sar (int a, int c) +{ + return a >> (c & 0x1f); +} + +unsigned int test_shr (unsigned int a, int c) +{ + return a >> (c & 0x1f); +} + +unsigned int test_rol (unsigned int a, int c) +{ + int z = c & 0x1f; + return (a << z) | (a >> (32 - z)); +} + +unsigned int test_ror (unsigned int a, int c) +{ + int z = c & 0x1f; + return (a >> z) | (a << (32 - z)); +} + +/* { dg-final { scan-assembler-not "and" } } */