| Message ID | 1472748665-47774-3-git-send-email-Zubair.Kakakhel@imgtec.com |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | David Miller |
| Headers | show |
Hi Zubair,
[auto build test WARNING on tip/irq/core]
[also build test WARNING on v4.8-rc4 next-20160825]
[cannot apply to linus/master linux/master]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Zubair-Lutfullah-Kakakhel/microblaze-MIPS-xilfpga-intc-and-peripheral/20160902-084739
config: microblaze-mmu_defconfig (attached as .config)
compiler: microblaze-linux-gcc (GCC) 4.9.0
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=microblaze
All warnings (new ones prefixed by >>):
drivers/irqchip/irq-axi-intc.c: In function 'xilinx_intc_of_init':
>> drivers/irqchip/irq-axi-intc.c:169:3: warning: format '%s' expects a matching 'char *' argument [-Wformat=]
pr_err("%s: Multiple instances of axi_intc aren't supported\n");
^
vim +169 drivers/irqchip/irq-axi-intc.c
153 .xlate = irq_domain_xlate_onetwocell,
154 .map = xintc_map,
155 };
156
157 static int __init xilinx_intc_of_init(struct device_node *intc,
158 struct device_node *parent)
159 {
160 u32 nr_irq;
161 int ret;
162 struct xintc_irq_chip *irqc;
163
164 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
165 if (!irqc)
166 return -ENOMEM;
167
168 if (xintc_irqc) {
> 169 pr_err("%s: Multiple instances of axi_intc aren't supported\n");
170 ret = -EINVAL;
171 goto err_alloc;
172 } else {
173 xintc_irqc = irqc;
174 }
175
176 irqc->base = of_iomap(intc, 0);
177 BUG_ON(!irqc->base);
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi, Thanks for the review. Comments inline. On 09/01/2016 06:15 PM, Marc Zyngier wrote: > On 01/09/16 17:50, Zubair Lutfullah Kakakhel wrote: >> The drivers read/write function handling is a bit quirky. >> And the irqmask is passed directly to the handler. >> >> Add a new irqchip struct to pass to the handler and >> cleanup read/write handling. >> >> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> >> >> --- >> V3 -> V4 >> Better error handling for kzalloc >> Erroring out if the axi intc is probed twice as that isn't >> supported >> ... >> static int __init xilinx_intc_of_init(struct device_node *intc, >> struct device_node *parent) >> { >> - u32 nr_irq, intr_mask; >> + u32 nr_irq; >> int ret; >> + struct xintc_irq_chip *irqc; >> + >> + irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); >> + if (!irqc) >> + return -ENOMEM; >> >> - intc_baseaddr = of_iomap(intc, 0); >> - BUG_ON(!intc_baseaddr); >> + if (xintc_irqc) { >> + pr_err("%s: Multiple instances of axi_intc aren't supported\n"); >> + ret = -EINVAL; >> + goto err_alloc; > > How about testing the variable first and error-ing early, rather than > performing the allocation and undoing it later? > Sure. Thanks >> + } else { >> + xintc_irqc = irqc; >> + } >> + >> + irqc->base = of_iomap(intc, 0); >> + BUG_ON(!irqc->base); >> >> ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); >> if (ret < 0) { >> pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); >> - return ret; >> + goto err_alloc; >> } >> >> - ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); >> + ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); >> if (ret < 0) { >> pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); >> - return ret; >> + goto err_alloc; >> } >> >> - if (intr_mask >> nr_irq) >> + if (irqc->intr_mask >> nr_irq) >> pr_warn("%s: mismatch in kind-of-intr param\n", __func__); >> >> pr_info("%s: num_irq=%d, edge=0x%x\n", >> - intc->full_name, nr_irq, intr_mask); >> + intc->full_name, nr_irq, irqc->intr_mask); >> >> - write_fn = intc_write32; >> - read_fn = intc_read32; >> + irqc->read = intc_read32; >> + irqc->write = intc_write32; >> >> /* >> * Disable all external interrupts until they are >> * explicity requested. >> */ >> - write_fn(0, intc_baseaddr + IER); >> + xintc_write(irqc, IER, 0); >> >> /* Acknowledge any pending interrupts just in case. */ >> - write_fn(0xffffffff, intc_baseaddr + IAR); >> + xintc_write(irqc, IAR, 0xffffffff); >> >> /* Turn on the Master Enable. */ >> - write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); >> - if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { >> - write_fn = intc_write32_be; >> - read_fn = intc_read32_be; >> - write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); >> + xintc_write(irqc, MER, MER_HIE | MER_ME); >> + if (!(xintc_read(irqc, MER) & (MER_HIE | MER_ME))) { >> + irqc->read = intc_read32_be; >> + irqc->write = intc_write32_be; >> + xintc_write(irqc, MER, MER_HIE | MER_ME); >> } >> >> - /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm >> - * lazy and Michal can clean it up to something nicer when he tests >> - * and commits this patch. ~~gcl */ >> root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, >> - (void *)intr_mask); >> + irqc); > > What if the domain allocation fails? You've now configured the HW for > something you can't use. What are the side effects? Hint: handle > everything that can fail first, and only then poke the HW. > Thanks for pointing it out. I'll add an error check. >> >> irq_set_default_host(root_domain); >> >> return 0; >> + >> +err_alloc: >> + xintc_irqc = NULL; >> + kfree(irqc); >> + return ret; >> + >> } >> >> IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); >> > > Instead of posting 3 versions in 3 days, please take the time to > correctly address the comments, and review your own code before > re-posting it. Rushing to get it merged for 4.9 is really not the best > approach. Apologies for the spam. Combination of some free time this week + window of opportunity. To be fair, AFAIK, this driver has lived in arch/microblaze without receiving a full thorough review by any irqchip maintainer. Hence the various missing bits. e.g. the root_domain error check didn't exist before. And I didn't see it. Regards, ZubairLK > > Thanks, > > M. >
diff --git a/drivers/irqchip/irq-axi-intc.c b/drivers/irqchip/irq-axi-intc.c index 90bec7d..7ab0762 100644 --- a/drivers/irqchip/irq-axi-intc.c +++ b/drivers/irqchip/irq-axi-intc.c @@ -16,8 +16,6 @@ #include <linux/io.h> #include <linux/bug.h> -static void __iomem *intc_baseaddr; - /* No one else should require these constants, so define them locally here. */ #define ISR 0x00 /* Interrupt Status Register */ #define IPR 0x04 /* Interrupt Pending Register */ @@ -31,8 +29,16 @@ static void __iomem *intc_baseaddr; #define MER_ME (1<<0) #define MER_HIE (1<<1) -static unsigned int (*read_fn)(void __iomem *); -static void (*write_fn)(u32, void __iomem *); +struct xintc_irq_chip { + void __iomem *base; + struct irq_domain *domain; + struct irq_chip chip; + u32 intr_mask; + unsigned int (*read)(void __iomem *iomem); + void (*write)(u32 data, void __iomem *iomem); +}; + +static struct xintc_irq_chip *xintc_irqc; static void intc_write32(u32 val, void __iomem *addr) { @@ -54,6 +60,18 @@ static unsigned int intc_read32_be(void __iomem *addr) return ioread32be(addr); } +static inline unsigned int xintc_read(struct xintc_irq_chip *xintc_irqc, + int reg) +{ + return xintc_irqc->read(xintc_irqc->base + reg); +} + +static inline void xintc_write(struct xintc_irq_chip *xintc_irqc, + int reg, u32 data) +{ + xintc_irqc->write(data, xintc_irqc->base + reg); +} + static void intc_enable_or_unmask(struct irq_data *d) { unsigned long mask = 1 << d->hwirq; @@ -65,21 +83,21 @@ static void intc_enable_or_unmask(struct irq_data *d) * acks the irq before calling the interrupt handler */ if (irqd_is_level_type(d)) - write_fn(mask, intc_baseaddr + IAR); + xintc_write(xintc_irqc, IAR, mask); - write_fn(mask, intc_baseaddr + SIE); + xintc_write(xintc_irqc, SIE, mask); } static void intc_disable_or_mask(struct irq_data *d) { pr_debug("disable: %ld\n", d->hwirq); - write_fn(1 << d->hwirq, intc_baseaddr + CIE); + xintc_write(xintc_irqc, CIE, 1 << d->hwirq); } static void intc_ack(struct irq_data *d) { pr_debug("ack: %ld\n", d->hwirq); - write_fn(1 << d->hwirq, intc_baseaddr + IAR); + xintc_write(xintc_irqc, IAR, 1 << d->hwirq); } static void intc_mask_ack(struct irq_data *d) @@ -87,8 +105,8 @@ static void intc_mask_ack(struct irq_data *d) unsigned long mask = 1 << d->hwirq; pr_debug("disable_and_ack: %ld\n", d->hwirq); - write_fn(mask, intc_baseaddr + CIE); - write_fn(mask, intc_baseaddr + IAR); + xintc_write(xintc_irqc, CIE, mask); + xintc_write(xintc_irqc, IAR, mask); } static struct irq_chip intc_dev = { @@ -105,7 +123,7 @@ unsigned int get_irq(void) { unsigned int hwirq, irq = -1; - hwirq = read_fn(intc_baseaddr + IVR); + hwirq = xintc_read(xintc_irqc, IVR); if (hwirq != -1U) irq = irq_find_mapping(root_domain, hwirq); @@ -116,7 +134,8 @@ unsigned int get_irq(void) static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { - u32 intr_mask = (u32)d->host_data; + struct xintc_irq_chip *irqc = d->host_data; + u32 intr_mask = irqc->intr_mask; if (intr_mask & (1 << hw)) { irq_set_chip_and_handler_name(irq, &intc_dev, @@ -138,59 +157,75 @@ static const struct irq_domain_ops xintc_irq_domain_ops = { static int __init xilinx_intc_of_init(struct device_node *intc, struct device_node *parent) { - u32 nr_irq, intr_mask; + u32 nr_irq; int ret; + struct xintc_irq_chip *irqc; + + irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); + if (!irqc) + return -ENOMEM; - intc_baseaddr = of_iomap(intc, 0); - BUG_ON(!intc_baseaddr); + if (xintc_irqc) { + pr_err("%s: Multiple instances of axi_intc aren't supported\n"); + ret = -EINVAL; + goto err_alloc; + } else { + xintc_irqc = irqc; + } + + irqc->base = of_iomap(intc, 0); + BUG_ON(!irqc->base); ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &nr_irq); if (ret < 0) { pr_err("%s: unable to read xlnx,num-intr-inputs\n", __func__); - return ret; + goto err_alloc; } - ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &intr_mask); + ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); if (ret < 0) { pr_err("%s: unable to read xlnx,kind-of-intr\n", __func__); - return ret; + goto err_alloc; } - if (intr_mask >> nr_irq) + if (irqc->intr_mask >> nr_irq) pr_warn("%s: mismatch in kind-of-intr param\n", __func__); pr_info("%s: num_irq=%d, edge=0x%x\n", - intc->full_name, nr_irq, intr_mask); + intc->full_name, nr_irq, irqc->intr_mask); - write_fn = intc_write32; - read_fn = intc_read32; + irqc->read = intc_read32; + irqc->write = intc_write32; /* * Disable all external interrupts until they are * explicity requested. */ - write_fn(0, intc_baseaddr + IER); + xintc_write(irqc, IER, 0); /* Acknowledge any pending interrupts just in case. */ - write_fn(0xffffffff, intc_baseaddr + IAR); + xintc_write(irqc, IAR, 0xffffffff); /* Turn on the Master Enable. */ - write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); - if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) { - write_fn = intc_write32_be; - read_fn = intc_read32_be; - write_fn(MER_HIE | MER_ME, intc_baseaddr + MER); + xintc_write(irqc, MER, MER_HIE | MER_ME); + if (!(xintc_read(irqc, MER) & (MER_HIE | MER_ME))) { + irqc->read = intc_read32_be; + irqc->write = intc_write32_be; + xintc_write(irqc, MER, MER_HIE | MER_ME); } - /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm - * lazy and Michal can clean it up to something nicer when he tests - * and commits this patch. ~~gcl */ root_domain = irq_domain_add_linear(intc, nr_irq, &xintc_irq_domain_ops, - (void *)intr_mask); + irqc); irq_set_default_host(root_domain); return 0; + +err_alloc: + xintc_irqc = NULL; + kfree(irqc); + return ret; + } IRQCHIP_DECLARE(xilinx_intc, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
The drivers read/write function handling is a bit quirky. And the irqmask is passed directly to the handler. Add a new irqchip struct to pass to the handler and cleanup read/write handling. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> --- V3 -> V4 Better error handling for kzalloc Erroring out if the axi intc is probed twice as that isn't supported V2 -> V3 New patch. Cleans up driver structure --- drivers/irqchip/irq-axi-intc.c | 101 +++++++++++++++++++++++++++-------------- 1 file changed, 68 insertions(+), 33 deletions(-)