| Message ID | 1472696063-17470-4-git-send-email-kever.yang@rock-chips.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Glass |
| Headers | show |
On 09/01/2016 04:14 AM, Kever Yang wrote: > The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, > add one variable in dwc3/dwc3_device struct to support 16 bit > UTMI+ interface on some SoCs like Rockchip rk3399. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > Changes in v4: > - use 1 bit for usb2_phyif_utmi_width instead of 5bit > > Changes in v3: > - Parse the DT for utmi+ interface width in dwc3 driver > > Changes in v2: > - use a variable to identify utmi+ bus width instead of CONFIG MACRO > > drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ > drivers/usb/dwc3/core.h | 12 ++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 85cc96a..8792f99 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -16,6 +16,7 @@ > > #include <common.h> > #include <malloc.h> > +#include <fdtdec.h> > #include <dwc3-uboot.h> > #include <asm/dma-mapping.h> > #include <linux/ioport.h> > @@ -29,6 +30,8 @@ > > #include "linux-compat.h" > > +DECLARE_GLOBAL_DATA_PTR; > + > static LIST_HEAD(dwc3_list); > /* -------------------------------------------------------------------------- */ > > @@ -388,6 +391,11 @@ static void dwc3_phy_setup(struct dwc3 *dwc) > if (dwc->dis_u2_susphy_quirk) > reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; > > + if (dwc->usb2_phyif_utmi_width == 1) { > + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; > + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; > + reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; > + } > dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); > > mdelay(100); > @@ -621,6 +629,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) > int ret; > > void *mem; > + const void *blob = gd->fdt_blob; > + int node; > > mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); > if (!mem) > @@ -682,6 +692,15 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) > > dwc->index = dwc3_dev->index; > > + node = fdt_node_offset_by_compatible(blob, -1, > + "rockchip,rk3399-xhci"); > + if (node < 0) > + debug("%s dwc3 node not found\n", __func__); > + else > + dwc->usb2_phyif_utmi_width = > + (fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1) > + == 16) ? 1 : 0; What happens if fdtdec_get_int() returns -1 here ? Is that an error? I just took a look into Linux and they use "phy_type" property to describe the PHY bus, with possible values being "utmi" "utmi_wide" "ulpi" etc . Do we need to invent new vendor-specific property ? See Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt in Linux for example. > dwc3_cache_hwparams(dwc); > > ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index 72d2fcd..7484d5f 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -74,6 +74,7 @@ > #define DWC3_GCTL 0xc110 > #define DWC3_GEVTEN 0xc114 > #define DWC3_GSTS 0xc118 > +#define DWC3_GUCTL1 0xc11c > #define DWC3_GSNPSID 0xc120 > #define DWC3_GGPIO 0xc124 > #define DWC3_GUID 0xc128 > @@ -162,7 +163,17 @@ > > /* Global USB2 PHY Configuration Register */ > #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) > +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) > #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) > +#define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) > +#define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) > +#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT (10) > +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << \ > + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) > +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ > + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) > +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ > + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) > > /* Global USB3 PIPE Control Register */ > #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) > @@ -813,6 +824,7 @@ struct dwc3 { > > unsigned tx_de_emphasis_quirk:1; > unsigned tx_de_emphasis:2; > + unsigned usb2_phyif_utmi_width:1; > int index; > struct list_head list; > }; >
Hi Marek, On 09/01/2016 05:09 PM, Marek Vasut wrote: > On 09/01/2016 04:14 AM, Kever Yang wrote: >> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, >> add one variable in dwc3/dwc3_device struct to support 16 bit >> UTMI+ interface on some SoCs like Rockchip rk3399. >> >> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >> --- >> >> Changes in v4: >> - use 1 bit for usb2_phyif_utmi_width instead of 5bit >> >> Changes in v3: >> - Parse the DT for utmi+ interface width in dwc3 driver >> >> Changes in v2: >> - use a variable to identify utmi+ bus width instead of CONFIG MACRO >> >> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ >> drivers/usb/dwc3/core.h | 12 ++++++++++++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >> index 85cc96a..8792f99 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -16,6 +16,7 @@ >> >> #include <common.h> >> #include <malloc.h> >> +#include <fdtdec.h> >> #include <dwc3-uboot.h> >> #include <asm/dma-mapping.h> >> #include <linux/ioport.h> >> @@ -29,6 +30,8 @@ >> >> #include "linux-compat.h" >> >> +DECLARE_GLOBAL_DATA_PTR; >> + >> static LIST_HEAD(dwc3_list); >> /* -------------------------------------------------------------------------- */ >> >> @@ -388,6 +391,11 @@ static void dwc3_phy_setup(struct dwc3 *dwc) >> if (dwc->dis_u2_susphy_quirk) >> reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; >> >> + if (dwc->usb2_phyif_utmi_width == 1) { >> + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; >> + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; >> + reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; >> + } >> dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); >> >> mdelay(100); >> @@ -621,6 +629,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) >> int ret; >> >> void *mem; >> + const void *blob = gd->fdt_blob; >> + int node; >> >> mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); >> if (!mem) >> @@ -682,6 +692,15 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) >> >> dwc->index = dwc3_dev->index; >> >> + node = fdt_node_offset_by_compatible(blob, -1, >> + "rockchip,rk3399-xhci"); >> + if (node < 0) >> + debug("%s dwc3 node not found\n", __func__); >> + else >> + dwc->usb2_phyif_utmi_width = >> + (fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1) >> + == 16) ? 1 : 0; > What happens if fdtdec_get_int() returns -1 here ? Is that an error? It may happen when the node is not defined, then we use 8bit as default, and we don't break any of origin source code. > > I just took a look into Linux and they use "phy_type" property to > describe the PHY bus, with possible values being "utmi" "utmi_wide" > "ulpi" etc . Do we need to invent new vendor-specific property ? > See Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt in Linux > for example. Well, I will parse "phy_type" for utmi width instead in next patch version. Thanks, - Kever > >> dwc3_cache_hwparams(dwc); >> >> ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); >> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h >> index 72d2fcd..7484d5f 100644 >> --- a/drivers/usb/dwc3/core.h >> +++ b/drivers/usb/dwc3/core.h >> @@ -74,6 +74,7 @@ >> #define DWC3_GCTL 0xc110 >> #define DWC3_GEVTEN 0xc114 >> #define DWC3_GSTS 0xc118 >> +#define DWC3_GUCTL1 0xc11c >> #define DWC3_GSNPSID 0xc120 >> #define DWC3_GGPIO 0xc124 >> #define DWC3_GUID 0xc128 >> @@ -162,7 +163,17 @@ >> >> /* Global USB2 PHY Configuration Register */ >> #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) >> +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) >> #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) >> +#define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) >> +#define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) >> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT (10) >> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << \ >> + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) >> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ >> + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) >> +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ >> + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) >> >> /* Global USB3 PIPE Control Register */ >> #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) >> @@ -813,6 +824,7 @@ struct dwc3 { >> >> unsigned tx_de_emphasis_quirk:1; >> unsigned tx_de_emphasis:2; >> + unsigned usb2_phyif_utmi_width:1; >> int index; >> struct list_head list; >> }; >> >
Kever, What is the status on this patch (and the encapsulating series)? This seems to be stuck in 'changes requested' for about a year now... Thanks, Philipp. On Thu, 1 Sep 2016, Kever Yang wrote: > The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, > add one variable in dwc3/dwc3_device struct to support 16 bit > UTMI+ interface on some SoCs like Rockchip rk3399. > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > Changes in v4: > - use 1 bit for usb2_phyif_utmi_width instead of 5bit > > Changes in v3: > - Parse the DT for utmi+ interface width in dwc3 driver > > Changes in v2: > - use a variable to identify utmi+ bus width instead of CONFIG MACRO > > drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ > drivers/usb/dwc3/core.h | 12 ++++++++++++ > 2 files changed, 31 insertions(+) >
Philipp,
I believe there are some request I think is not reasonable which
stop me from update new patch sets.
The usb/dwc3 is mess up now, separate in host mode and gadget mode, one
need init in board init
while another use DM. When I want to add a new feature like use 16bit
UTMI+ instead of 8bit(which suppose to be very very simple),
I don't think the maintainer have an idea where it should go and how it
should be, and the driver now
it's far away from upstream kernel.
I have send 4 patch set for this, everything should be clear, but...
Thanks,
- Kever
On 09/11/2017 09:30 PM, Philipp Tomsich wrote:
>
> Kever,
>
> What is the status on this patch (and the encapsulating series)?
> This seems to be stuck in 'changes requested' for about a year now...
>
> Thanks,
> Philipp.
>
> On Thu, 1 Sep 2016, Kever Yang wrote:
>
>> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
>> add one variable in dwc3/dwc3_device struct to support 16 bit
>> UTMI+ interface on some SoCs like Rockchip rk3399.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> Changes in v4:
>> - use 1 bit for usb2_phyif_utmi_width instead of 5bit
>>
>> Changes in v3:
>> - Parse the DT for utmi+ interface width in dwc3 driver
>>
>> Changes in v2:
>> - use a variable to identify utmi+ bus width instead of CONFIG MACRO
>>
>> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++
>> drivers/usb/dwc3/core.h | 12 ++++++++++++
>> 2 files changed, 31 insertions(+)
>>
>
Marek, do you know whether there's an update of the DWC3 driver planned to get us back in sync with the kernel driver? Thanks, Philipp. > On 12 Sep 2017, at 07:02, Kever Yang <kever.yang@rock-chips.com> wrote: > > Philipp, > > I believe there are some request I think is not reasonable which stop me from update new patch sets. > > The usb/dwc3 is mess up now, separate in host mode and gadget mode, one need init in board init > > while another use DM. When I want to add a new feature like use 16bit UTMI+ instead of 8bit(which suppose to be very very simple), > > I don't think the maintainer have an idea where it should go and how it should be, and the driver now > > it's far away from upstream kernel. > > I have send 4 patch set for this, everything should be clear, but... > > > > Thanks, > - Kever > On 09/11/2017 09:30 PM, Philipp Tomsich wrote: >> >> Kever, >> >> What is the status on this patch (and the encapsulating series)? >> This seems to be stuck in 'changes requested' for about a year now... >> >> Thanks, >> Philipp. >> >> On Thu, 1 Sep 2016, Kever Yang wrote: >> >>> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, >>> add one variable in dwc3/dwc3_device struct to support 16 bit >>> UTMI+ interface on some SoCs like Rockchip rk3399. >>> >>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >>> --- >>> >>> Changes in v4: >>> - use 1 bit for usb2_phyif_utmi_width instead of 5bit >>> >>> Changes in v3: >>> - Parse the DT for utmi+ interface width in dwc3 driver >>> >>> Changes in v2: >>> - use a variable to identify utmi+ bus width instead of CONFIG MACRO >>> >>> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ >>> drivers/usb/dwc3/core.h | 12 ++++++++++++ >>> 2 files changed, 31 insertions(+) >>> >> > >
On 09/12/2017 11:09 AM, Dr. Philipp Tomsich wrote: > Marek, > > do you know whether there's an update of the DWC3 driver planned to get us back in sync with the kernel driver? To my knowledge, no. Patches welcome. btw please stop top-posting > Thanks, > Philipp. > > >> On 12 Sep 2017, at 07:02, Kever Yang <kever.yang@rock-chips.com> wrote: >> >> Philipp, >> >> I believe there are some request I think is not reasonable which stop me from update new patch sets. >> >> The usb/dwc3 is mess up now, separate in host mode and gadget mode, one need init in board init >> >> while another use DM. When I want to add a new feature like use 16bit UTMI+ instead of 8bit(which suppose to be very very simple), >> >> I don't think the maintainer have an idea where it should go and how it should be, and the driver now >> >> it's far away from upstream kernel. >> >> I have send 4 patch set for this, everything should be clear, but... >> >> >> >> Thanks, >> - Kever >> On 09/11/2017 09:30 PM, Philipp Tomsich wrote: >>> >>> Kever, >>> >>> What is the status on this patch (and the encapsulating series)? >>> This seems to be stuck in 'changes requested' for about a year now... >>> >>> Thanks, >>> Philipp. >>> >>> On Thu, 1 Sep 2016, Kever Yang wrote: >>> >>>> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, >>>> add one variable in dwc3/dwc3_device struct to support 16 bit >>>> UTMI+ interface on some SoCs like Rockchip rk3399. >>>> >>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >>>> --- >>>> >>>> Changes in v4: >>>> - use 1 bit for usb2_phyif_utmi_width instead of 5bit >>>> >>>> Changes in v3: >>>> - Parse the DT for utmi+ interface width in dwc3 driver >>>> >>>> Changes in v2: >>>> - use a variable to identify utmi+ bus width instead of CONFIG MACRO >>>> >>>> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ >>>> drivers/usb/dwc3/core.h | 12 ++++++++++++ >>>> 2 files changed, 31 insertions(+) >>>> >>> >> >> >
Kever, > On 12 Sep 2017, at 12:22, Marek Vasut <marex@denx.de> wrote: > > On 09/12/2017 11:09 AM, Dr. Philipp Tomsich wrote: >> Marek, >> >> do you know whether there's an update of the DWC3 driver planned to get us back in sync with the kernel driver? > > To my knowledge, no. Patches welcome. Could you summarise (for everyone involved) what the impact of this series not being merged is in terms of functionality? Once everyone is aware of what the objectives are, we can then try to revive the discussion and agree on a specific set of changes (to the series) to move forward... Cheers, Philipp. > >> Thanks, >> Philipp. >> >> >>> On 12 Sep 2017, at 07:02, Kever Yang <kever.yang@rock-chips.com> wrote: >>> >>> Philipp, >>> >>> I believe there are some request I think is not reasonable which stop me from update new patch sets. >>> >>> The usb/dwc3 is mess up now, separate in host mode and gadget mode, one need init in board init >>> >>> while another use DM. When I want to add a new feature like use 16bit UTMI+ instead of 8bit(which suppose to be very very simple), >>> >>> I don't think the maintainer have an idea where it should go and how it should be, and the driver now >>> >>> it's far away from upstream kernel. >>> >>> I have send 4 patch set for this, everything should be clear, but... >>> >>> >>> >>> Thanks, >>> - Kever >>> On 09/11/2017 09:30 PM, Philipp Tomsich wrote: >>>> >>>> Kever, >>>> >>>> What is the status on this patch (and the encapsulating series)? >>>> This seems to be stuck in 'changes requested' for about a year now... >>>> >>>> Thanks, >>>> Philipp. >>>> >>>> On Thu, 1 Sep 2016, Kever Yang wrote: >>>> >>>>> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, >>>>> add one variable in dwc3/dwc3_device struct to support 16 bit >>>>> UTMI+ interface on some SoCs like Rockchip rk3399. >>>>> >>>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> >>>>> --- >>>>> >>>>> Changes in v4: >>>>> - use 1 bit for usb2_phyif_utmi_width instead of 5bit >>>>> >>>>> Changes in v3: >>>>> - Parse the DT for utmi+ interface width in dwc3 driver >>>>> >>>>> Changes in v2: >>>>> - use a variable to identify utmi+ bus width instead of CONFIG MACRO >>>>> >>>>> drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ >>>>> drivers/usb/dwc3/core.h | 12 ++++++++++++ >>>>> 2 files changed, 31 insertions(+) >>>>> >>>> >>> >>> >> > > > -- > Best regards, > Marek Vasut
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 85cc96a..8792f99 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -16,6 +16,7 @@ #include <common.h> #include <malloc.h> +#include <fdtdec.h> #include <dwc3-uboot.h> #include <asm/dma-mapping.h> #include <linux/ioport.h> @@ -29,6 +30,8 @@ #include "linux-compat.h" +DECLARE_GLOBAL_DATA_PTR; + static LIST_HEAD(dwc3_list); /* -------------------------------------------------------------------------- */ @@ -388,6 +391,11 @@ static void dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u2_susphy_quirk) reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + if (dwc->usb2_phyif_utmi_width == 1) { + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + reg |= DWC3_GUSB2PHYCFG_PHYIF_16BIT; + } dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); mdelay(100); @@ -621,6 +629,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) int ret; void *mem; + const void *blob = gd->fdt_blob; + int node; mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); if (!mem) @@ -682,6 +692,15 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) dwc->index = dwc3_dev->index; + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3399-xhci"); + if (node < 0) + debug("%s dwc3 node not found\n", __func__); + else + dwc->usb2_phyif_utmi_width = + (fdtdec_get_int(blob, node, "snps,phyif-utmi-bits", -1) + == 16) ? 1 : 0; + dwc3_cache_hwparams(dwc); ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 72d2fcd..7484d5f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -74,6 +74,7 @@ #define DWC3_GCTL 0xc110 #define DWC3_GEVTEN 0xc114 #define DWC3_GSTS 0xc118 +#define DWC3_GUCTL1 0xc11c #define DWC3_GSNPSID 0xc120 #define DWC3_GGPIO 0xc124 #define DWC3_GUID 0xc128 @@ -162,7 +163,17 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYIF_8BIT (0 << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_16BIT (1 << 3) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT (10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT) /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) @@ -813,6 +824,7 @@ struct dwc3 { unsigned tx_de_emphasis_quirk:1; unsigned tx_de_emphasis:2; + unsigned usb2_phyif_utmi_width:1; int index; struct list_head list; };
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY, add one variable in dwc3/dwc3_device struct to support 16 bit UTMI+ interface on some SoCs like Rockchip rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- Changes in v4: - use 1 bit for usb2_phyif_utmi_width instead of 5bit Changes in v3: - Parse the DT for utmi+ interface width in dwc3 driver Changes in v2: - use a variable to identify utmi+ bus width instead of CONFIG MACRO drivers/usb/dwc3/core.c | 19 +++++++++++++++++++ drivers/usb/dwc3/core.h | 12 ++++++++++++ 2 files changed, 31 insertions(+)