@@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
volatile struct mmdc_p_regs *mmdc0;
volatile struct mmdc_p_regs *mmdc1;
u32 val;
- u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+ u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
@@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
MMDC1(mpzqhwctrl, val);
/* Step 12: Configure and activate periodic refresh */
- mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
- (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
+ if (!is_mx6ul()) {
+ refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */
+ refr = 7; /* REFR: Refresh Rate - 8 refreshes */
+ } else {
+ refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */
+ refr = 1; /* REFR: Refresh Rate - 2 refreshes */
+ }
+ mmdc0->mdref = (refsel << 14) | (refr << 11);
/* Step 13: Deassert config request - init complete */
mmdc0->mdscr = 0x00000000;