| Message ID | 1472210916-36539-8-git-send-email-Qianyu.Gong@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
On 08/26/2016 04:40 AM, Gong Qianyu wrote: > From: Shaohui Xie <Shaohui.Xie@nxp.com> > > So to fix SATA CRC error. Does ECC cause the CRC error? Please explain more what you are doing in this patch. York
> -----Original Message----- > From: york sun > Sent: Saturday, August 27, 2016 12:08 AM > To: Qianyu Gong <qianyu.gong@nxp.com>; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Mingkai Hu > <mingkai.hu@nxp.com>; Shaohui Xie <shaohui.xie@nxp.com>; Zhiqiang Hou > <zhiqiang.hou@nxp.com>; Wenbin Song <wenbin.song@nxp.com> > Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR > > On 08/26/2016 04:40 AM, Gong Qianyu wrote: > > From: Shaohui Xie <Shaohui.Xie@nxp.com> > > > > So to fix SATA CRC error. > > Does ECC cause the CRC error? Please explain more what you are doing in this > patch. [S.H] We only know disable ECC can fix CRC error which provided by validation team As a workaround, the root cause is not clear. Maybe we can drop it for now, there might be a better solution for this issue in future, or the solution is still the same, but we know exactly what is going on. Thanks, Shaohui
> -----Original Message----- > From: Shaohui Xie > Sent: Monday, August 29, 2016 12:45 PM > To: york sun <york.sun@nxp.com>; Qianyu Gong <qianyu.gong@nxp.com>; > u-boot@lists.denx.de > Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Mingkai Hu > <mingkai.hu@nxp.com>; Zhiqiang Hou <zhiqiang.hou@nxp.com>; Wenbin > Song <wenbin.song@nxp.com> > Subject: RE: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR > > > -----Original Message----- > > From: york sun > > Sent: Saturday, August 27, 2016 12:08 AM > > To: Qianyu Gong <qianyu.gong@nxp.com>; u-boot@lists.denx.de > > Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>; Mingkai Hu > > <mingkai.hu@nxp.com>; Shaohui Xie <shaohui.xie@nxp.com>; Zhiqiang > Hou > > <zhiqiang.hou@nxp.com>; Wenbin Song <wenbin.song@nxp.com> > > Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR > > > > On 08/26/2016 04:40 AM, Gong Qianyu wrote: > > > From: Shaohui Xie <Shaohui.Xie@nxp.com> > > > > > > So to fix SATA CRC error. > > > > Does ECC cause the CRC error? Please explain more what you are doing > > in this patch. > [S.H] We only know disable ECC can fix CRC error which provided by > validation team As a workaround, the root cause is not clear. > > Maybe we can drop it for now, there might be a better solution for this issue > in future, or the solution is still the same, but we know exactly what is going > on. > > Thanks, > Shaohui Maybe we keep this patch and add the description in the git log, and remove the Disabling ECC when the root cause has found. At lease, disabling ECC can make the SATA working. Thanks, Mingkai
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..f1c6964 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -22,6 +22,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define SATA_ECC_REG_ADDR 0x20140520 +#define SATA_ECC_DISABLE 0x80000000 + bool soc_has_dp_ddr(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -222,6 +225,9 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; +#ifdef CONFIG_LS1046A + out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); +#endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);