| Message ID | 1472120716-20140-1-git-send-email-ravibabu@ti.com |
|---|---|
| State | Rejected |
| Delegated to: | Tom Rini |
| Headers | show |
On Thu, Aug 25, 2016 at 03:55:16PM +0530, Ravi Babu wrote: > The CONFIG_SYS_CACHELINE_SIZE is not defined for > some of the platforms due to which buildman iill > fail for these platforms. > > Fixing this issue in generic way in Kconfig by > selecting cacheline size based on arm processor type. > > This patch is based on linux kernel commit 5637a126 > > Signed-off-by: Ravi Babu <ravibabu@ti.com> > Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Please see https://patchwork.ozlabs.org/patch/661424/ thanks!
Hi Tom, > On Thu, Aug 25, 2016 at 03:55:16PM +0530, Ravi Babu wrote: > > > The CONFIG_SYS_CACHELINE_SIZE is not defined for > > some of the platforms due to which buildman iill > > fail for these platforms. > > > > Fixing this issue in generic way in Kconfig by > > selecting cacheline size based on arm processor type. > > > > This patch is based on linux kernel commit 5637a126 > > > > Signed-off-by: Ravi Babu <ravibabu@ti.com> > > Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> > > Please see https://patchwork.ozlabs.org/patch/661424/ thanks! > Seems OK :-). Thanks for providing the patch.
Hi Tom >> >> > The CONFIG_SYS_CACHELINE_SIZE is not defined for some of the >> > platforms due to which buildman iill fail for these platforms. >> > >> > Fixing this issue in generic way in Kconfig by selecting cacheline >> > size based on arm processor type. >> > >> > This patch is based on linux kernel commit 5637a126 >> > >> > Signed-off-by: Ravi Babu <ravibabu@ti.com> >> > Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> >> >> Please see https://patchwork.ozlabs.org/patch/661424/ thanks! >> >Seems OK :-). >Thanks for providing the patch. I missed this patch https://patchwork.ozlabs.org/patch/661424/ I checked with this patch running buildman on SPL-DFU patches, it succeeded. Thanks. Regards Ravi
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..776d3b7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -42,6 +42,17 @@ config CPU_V7 select HAS_VBAR select HAS_THUMB2 +config ARM_L1_CACHE_SHIFT_6 + bool + default y if CPU_V7 + help + Setting ARM L1 cache line size to 64 Bytes. + +config ARM_L1_CACHE_SHIFT + int + default 6 if ARM_L1_CACHE_SHIFT_6 + default 5 + config CPU_V7M bool select HAS_THUMB2 diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a20702e..fb3b59b 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -60,6 +60,7 @@ #include <linux/types.h> #include <asm/io.h> #include <asm/barriers.h> +#include <asm/cache.h> /* * Workaround for ARM errata # 798870 diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 16e65c3..7c57422 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -47,6 +47,11 @@ void dram_bank_mmu_setup(int bank); * use that value for aligning DMA buffers unless the board config has specified * an alternate cache line size. */ +#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE (1 << L1_CACHE_SHIFT) +#endif + #ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #else