| Message ID | 1471596759-3396-3-git-send-email-aneesh.kumar@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote: > Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> > --- > arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 1 + > arch/powerpc/mm/tlb-radix.c | 15 > +++++++++++++++ > 2 files changed, 16 insertions(+) Don't we need two ? One for partition scoped and one for process scoped ? > diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > index 65037762b120..a9e19cb2f7c5 100644 > --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct > mm_struct *mm, unsigned long vmad > extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned > long gpa, > unsigned long page_size); > extern void radix__flush_tlb_lpid(unsigned long lpid); > +extern void radix__flush_tlb_all(void); > #endif > diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb- > radix.c > index 48df05ef5231..517feb47ebe4 100644 > --- a/arch/powerpc/mm/tlb-radix.c > +++ b/arch/powerpc/mm/tlb-radix.c > @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct > vm_area_struct *vma, > radix__flush_tlb_range_psize(vma->vm_mm, start, end, > MMU_PAGE_2M); > } > EXPORT_SYMBOL(radix__flush_pmd_tlb_range); > + > +void radix__flush_tlb_all(void) > +{ > + unsigned long rb,prs,r; > + unsigned long ric = RIC_FLUSH_ALL; > + > + rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */ > + prs = 0; /* partition scoped */ > + r = 1; /* raidx format */ > + > + asm volatile("ptesync": : :"memory"); > + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) > + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) > : "memory"); > + asm volatile("eieio; tlbsync; ptesync": : :"memory"); > +}
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes: > On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote: >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> >> --- >> arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 1 + >> arch/powerpc/mm/tlb-radix.c | 15 >> +++++++++++++++ >> 2 files changed, 16 insertions(+) > > Don't we need two ? One for partition scoped and one for process scoped > ? With invalid selector value 3 (IS = 3), we will invalidate all entries when executed with MSR[HV] = 1. I guess that should take out all the translation cache, including implementation dependent one ? Also note thar PRS = 0. ie, we are partition scoped. ie, we are doing invalidate with PRS =0, IS = 3 HV = 1 RIC = 2 > >> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h >> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h >> index 65037762b120..a9e19cb2f7c5 100644 >> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h >> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h >> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct >> mm_struct *mm, unsigned long vmad >> extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned >> long gpa, >> unsigned long page_size); >> extern void radix__flush_tlb_lpid(unsigned long lpid); >> +extern void radix__flush_tlb_all(void); >> #endif >> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb- >> radix.c >> index 48df05ef5231..517feb47ebe4 100644 >> --- a/arch/powerpc/mm/tlb-radix.c >> +++ b/arch/powerpc/mm/tlb-radix.c >> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct >> vm_area_struct *vma, >> radix__flush_tlb_range_psize(vma->vm_mm, start, end, >> MMU_PAGE_2M); >> } >> EXPORT_SYMBOL(radix__flush_pmd_tlb_range); >> + >> +void radix__flush_tlb_all(void) >> +{ >> + unsigned long rb,prs,r; >> + unsigned long ric = RIC_FLUSH_ALL; >> + >> + rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */ >> + prs = 0; /* partition scoped */ >> + r = 1; /* raidx format */ >> + >> + asm volatile("ptesync": : :"memory"); >> + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) >> + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) >> : "memory"); >> + asm volatile("eieio; tlbsync; ptesync": : :"memory"); >> +}
On Mon, Aug 22, 2016 at 11:41:13AM +0530, Aneesh Kumar K.V wrote: > Benjamin Herrenschmidt <benh@kernel.crashing.org> writes: > > > On Fri, 2016-08-19 at 14:22 +0530, Aneesh Kumar K.V wrote: > >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> > >> --- > >> arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 1 + > >> arch/powerpc/mm/tlb-radix.c | 15 > >> +++++++++++++++ > >> 2 files changed, 16 insertions(+) > > > > Don't we need two ? One for partition scoped and one for process scoped > > ? > > > With invalid selector value 3 (IS = 3), we will invalidate all entries > when executed with MSR[HV] = 1. I guess that should take out all the > translation cache, including implementation dependent one ? > I think Ben might be right, we probably need two. We probably want to invlidate the process scoped ones first followed by partition scope. I could not find anything in the documentation that said partition scope flush implied process scope flush. > Also note thar PRS = 0. ie, we are partition scoped. ie, we are doing > invalidate with > > PRS =0, IS = 3 HV = 1 RIC = 2 > > > > >> diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > >> b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > >> index 65037762b120..a9e19cb2f7c5 100644 > >> --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > >> +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h > >> @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct > >> mm_struct *mm, unsigned long vmad > >> extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned > >> long gpa, > >> unsigned long page_size); > >> extern void radix__flush_tlb_lpid(unsigned long lpid); > >> +extern void radix__flush_tlb_all(void); > >> #endif > >> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb- > >> radix.c > >> index 48df05ef5231..517feb47ebe4 100644 > >> --- a/arch/powerpc/mm/tlb-radix.c > >> +++ b/arch/powerpc/mm/tlb-radix.c > >> @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct > >> vm_area_struct *vma, > >> radix__flush_tlb_range_psize(vma->vm_mm, start, end, > >> MMU_PAGE_2M); > >> } > >> EXPORT_SYMBOL(radix__flush_pmd_tlb_range); > >> + > >> +void radix__flush_tlb_all(void) > >> +{ > >> + unsigned long rb,prs,r; > >> + unsigned long ric = RIC_FLUSH_ALL; > >> + > >> + rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */ > >> + prs = 0; /* partition scoped */ > >> + r = 1; /* raidx format */ ^^ radix > >> + > >> + asm volatile("ptesync": : :"memory"); > >> + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) > >> + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) > >> : "memory"); > >> + asm volatile("eieio; tlbsync; ptesync": : :"memory"); > >> +} > Balbir Singh.
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h index 65037762b120..a9e19cb2f7c5 100644 --- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h +++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h @@ -41,4 +41,5 @@ extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmad extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa, unsigned long page_size); extern void radix__flush_tlb_lpid(unsigned long lpid); +extern void radix__flush_tlb_all(void); #endif diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c index 48df05ef5231..517feb47ebe4 100644 --- a/arch/powerpc/mm/tlb-radix.c +++ b/arch/powerpc/mm/tlb-radix.c @@ -400,3 +400,18 @@ void radix__flush_pmd_tlb_range(struct vm_area_struct *vma, radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M); } EXPORT_SYMBOL(radix__flush_pmd_tlb_range); + +void radix__flush_tlb_all(void) +{ + unsigned long rb,prs,r; + unsigned long ric = RIC_FLUSH_ALL; + + rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */ + prs = 0; /* partition scoped */ + r = 1; /* raidx format */ + + asm volatile("ptesync": : :"memory"); + asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1) + : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory"); + asm volatile("eieio; tlbsync; ptesync": : :"memory"); +}
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> --- arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 1 + arch/powerpc/mm/tlb-radix.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+)