From patchwork Wed Sep 29 09:47:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejas Belagod X-Patchwork-Id: 66061 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 51024B6F10 for ; Wed, 29 Sep 2010 19:47:20 +1000 (EST) Received: (qmail 6138 invoked by alias); 29 Sep 2010 09:47:19 -0000 Received: (qmail 6128 invoked by uid 22791); 29 Sep 2010 09:47:18 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL, BAYES_00, TW_VM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (217.140.96.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 29 Sep 2010 09:47:05 +0000 Received: from cam-owa2.Emea.Arm.com (cam-owa2.emea.arm.com [10.1.105.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id o8T9hsF9018888 for ; Wed, 29 Sep 2010 10:43:54 +0100 (BST) Received: from [10.1.67.25] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 29 Sep 2010 10:47:01 +0100 Subject: [PATCH, ARM] Fix ICE (PR target/45805). From: Tejas Belagod To: gcc-patches@gcc.gnu.org Date: Wed, 29 Sep 2010 10:47:01 +0100 Message-Id: <1285753621.22296.3.camel@e102484-lin.cambridge.arm.com> Mime-Version: 1.0 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch fixes bug PR target/45805. A missing constraint specifier in patterns for vmovl and vmovn was causing the compiler to ICE by matching memory operands instead of the intended register operands. A 'w' in the constraint specifier fixes the ICE. Also the instruction templates for vmovl, vmovn and vmull have been fixed by adding intended register specifiers. OK? --- Tejas Belagod ARM. gcc/ 2010-09-29 Tejas Belagod * config/arm/neon.md (neon_unpack_): Add 'w' to constraint, add register specifier in instruction template. (neon_vec_pack_trunc_): Likewise. (neon_vec_mult_): Add register specifier to instruction template. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 3bb74a2..1e88981 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5314,9 +5314,9 @@ ;; Vectorize for non-neon-quad case (define_insn "neon_unpack_" [(set (match_operand: 0 "register_operand" "=w") - (SE: (match_operand:VDI 1 "register_operand" "")))] + (SE: (match_operand:VDI 1 "register_operand" "w")))] "TARGET_NEON" - "vmovl. %q0, %1" + "vmovl. %q0, %P1" [(set_attr "neon_type" "neon_shift_1")] ) @@ -5353,7 +5353,7 @@ (SE: (match_operand:VDI 2 "register_operand" "w"))))] "TARGET_NEON" - "vmull. %q0, %1, %2" + "vmull. %q0, %P1, %P2" [(set_attr "neon_type" "neon_shift_1")] ) @@ -5402,9 +5402,9 @@ ;; For the non-quad case. (define_insn "neon_vec_pack_trunc_" [(set (match_operand: 0 "register_operand" "=w") - (truncate: (match_operand:VN 1 "register_operand" "")))] + (truncate: (match_operand:VN 1 "register_operand" "w")))] "TARGET_NEON" - "vmovn.i\t%0, %q1" + "vmovn.i\t%P0, %q1" [(set_attr "neon_type" "neon_shift_1")] )