From patchwork Sun Sep 26 16:35:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 65793 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id BDBE3B6F06 for ; Mon, 27 Sep 2010 02:35:15 +1000 (EST) Received: (qmail 8293 invoked by alias); 26 Sep 2010 16:35:11 -0000 Received: (qmail 8132 invoked by uid 22791); 26 Sep 2010 16:35:08 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-qy0-f175.google.com (HELO mail-qy0-f175.google.com) (209.85.216.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 26 Sep 2010 16:35:03 +0000 Received: by qyk31 with SMTP id 31so148228qyk.20 for ; Sun, 26 Sep 2010 09:35:00 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.228.137 with SMTP id je9mr4693868qcb.219.1285518900783; Sun, 26 Sep 2010 09:35:00 -0700 (PDT) Received: by 10.229.84.4 with HTTP; Sun, 26 Sep 2010 09:35:00 -0700 (PDT) Date: Sun, 26 Sep 2010 18:35:00 +0200 Message-ID: Subject: Re: [patch i386]: Change stack probing and allocation implementation From: Uros Bizjak To: gcc-patches@gcc.gnu.org Cc: Richard Henderson , Kai Tietz Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! > >> 2010-08-19 Kai Tietz > >> > >> * config/i386/cygwin.asm (___chkstk_ms): New. > >> * config/i386/i386.c (override_options): Replace > >> gen_allocate_stack_worker_,, by gen_allocate_stack_worker_probe_,,. > >> (ix86_expand_prologue): Adjust probed stack allocation. > >> * config/i386/i386.md (define_insn "allocate_stack_worker_32): Removed. > >> (define_insn "allocate_stack_worker_64): Removed. > >> (define_insn "allocate_stack_worker_probe_32): New. > >> (define_insn "allocate_stack_worker_probe_64): New. > >> (allocate_stack): Adjust probed stack allocation. > > I altered the patch a bit. Tidied up the .md changes with macros, > tidied up the assembly file with multiple object files and dwarf2 > unwind info. Adjusted the prologue code to use the value in eax. > +(define_insn "pro_epilogue_adjust_stack__2" > + [(set (match_operand:P 0 "register_operand" "=r") > + (plus:P (match_operand:DI 1 "register_operand" "0") > + (match_operand:DI 2 "register_operand" "r"))) > (clobber (reg:CC FLAGS_REG)) > (clobber (mem:BLK (scratch)))] Hm, this can't be right for Pmode == SImode. Alternatively, it is now possible to merge pro_epilogue_..._1 and pro_epilogue_,,,_2 into: (define_insn "pro_epilogue_adjust_stack__add" [(set (match_operand:P 0 "register_operand" "=r,r") (plus:P (match_operand:P 1 "register_operand" "0,r") (match_operand:P 2 "" "r,l"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "" { switch (get_attr_type (insn)) { case TYPE_IMOV: return "mov{}\t{%1, %0|%0, %1}"; case TYPE_ALU: gcc_assert (rtx_equal_p (operands[0], operands[1])); if (x86_maybe_negate_const_int (&operands[2], mode)) return "sub{}\t{%2, %0|%0, %2}"; return "add{}\t{%2, %0|%0, %2}"; default: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); return "lea{}\t{%a2, %0|%0, %a2}"; } } [(set (attr "type") (cond [(and (eq_attr "alternative" "0") (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) (const_string "alu") (match_operand: 2 "const0_operand" "") (const_string "imov") ] (const_string "lea"))) (set (attr "length_immediate") (cond [(eq_attr "type" "imov") (const_string "0") (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) (const_string "1") ] (const_string "*"))) (set_attr "mode" "")]) Attached [RFC] patch implements this merge, and some related cleanups involving renames and indirect functions. Patch was tested on x86_64-pc-linux-gnu without regressions. Uros. Index: i386.md =================================================================== --- i386.md (revision 164630) +++ i386.md (working copy) @@ -16246,10 +16246,10 @@ ;; ;; in proper program order. -(define_insn "pro_epilogue_adjust_stack__1" +(define_insn "pro_epilogue_adjust_stack__add" [(set (match_operand:P 0 "register_operand" "=r,r") (plus:P (match_operand:P 1 "register_operand" "0,r") - (match_operand:P 2 "" ","))) + (match_operand:P 2 "" "r,l"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "" @@ -16289,18 +16289,7 @@ (const_string "*"))) (set_attr "mode" "")]) -(define_insn "pro_epilogue_adjust_stack__2" - [(set (match_operand:P 0 "register_operand" "=r") - (plus:P (match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "register_operand" "r"))) - (clobber (reg:CC FLAGS_REG)) - (clobber (mem:BLK (scratch)))] - "" - "add{}\t{%2, %0|%0, %2}" - [(set_attr "type" "alu") - (set_attr "mode" "")]) - -(define_insn "pro_epilogue_adjust_stack__3" +(define_insn "pro_epilogue_adjust_stack__sub" [(set (match_operand:P 0 "register_operand" "=r") (minus:P (match_operand:P 1 "register_operand" "0") (match_operand:P 2 "register_operand" "r"))) Index: i386.c =================================================================== --- i386.c (revision 164630) +++ i386.c (working copy) @@ -8777,9 +8777,11 @@ pro_epilogue_adjust_stack (rtx dest, rtx rtx insn; if (! TARGET_64BIT) - insn = emit_insn (gen_pro_epilogue_adjust_stack_si_1 (dest, src, offset)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_si_add (dest, + src, offset)); else if (x86_64_immediate_operand (offset, DImode)) - insn = emit_insn (gen_pro_epilogue_adjust_stack_di_1 (dest, src, offset)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, + src, offset)); else { rtx tmp; @@ -8796,7 +8798,7 @@ pro_epilogue_adjust_stack (rtx dest, rtx insn = emit_insn (gen_rtx_SET (DImode, tmp, offset)); if (style < 0) RTX_FRAME_RELATED_P (insn) = 1; - insn = emit_insn (gen_pro_epilogue_adjust_stack_di_2 (dest, src, tmp)); + insn = emit_insn (gen_pro_epilogue_adjust_stack_di_add (dest, src, tmp)); } if (style >= 0) @@ -9698,6 +9700,8 @@ ix86_expand_prologue (void) { rtx eax = gen_rtx_REG (Pmode, AX_REG); rtx r10 = NULL; + rtx (*adjust_stack_insn)(rtx, rtx, rtx); + bool eax_live = false; bool r10_live = false; @@ -9722,13 +9726,12 @@ ix86_expand_prologue (void) emit_insn (ix86_gen_allocate_stack_worker (eax, eax)); /* Use the fact that AX still contains ALLOCATE. */ - if (TARGET_64BIT) - insn = gen_pro_epilogue_adjust_stack_di_3 (stack_pointer_rtx, - stack_pointer_rtx, eax); - else - insn = gen_pro_epilogue_adjust_stack_si_3 (stack_pointer_rtx, - stack_pointer_rtx, eax); - insn = emit_insn (insn); + adjust_stack_insn = (TARGET_64BIT + ? gen_pro_epilogue_adjust_stack_di_sub + : gen_pro_epilogue_adjust_stack_si_sub); + + insn = emit_insn (adjust_stack_insn (stack_pointer_rtx, + stack_pointer_rtx, eax)); if (m->fs.cfa_reg == stack_pointer_rtx) {