From patchwork Wed Aug 3 03:10:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 655236 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3s3yqt6mdlz9s5g for ; Wed, 3 Aug 2016 13:15:22 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=ZIx9+/Ql; dkim-atps=neutral Received: from localhost ([::1]:59937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUmeN-0001XH-Ou for incoming@patchwork.ozlabs.org; Tue, 02 Aug 2016 23:15:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48739) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUma8-0005jM-Ve for qemu-devel@nongnu.org; Tue, 02 Aug 2016 23:10:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bUma5-0006tq-Ue for qemu-devel@nongnu.org; Tue, 02 Aug 2016 23:10:55 -0400 Received: from mail-pa0-x244.google.com ([2607:f8b0:400e:c03::244]:33751) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUma5-0006tj-K9 for qemu-devel@nongnu.org; Tue, 02 Aug 2016 23:10:53 -0400 Received: by mail-pa0-x244.google.com with SMTP id q2so13132193pap.0 for ; Tue, 02 Aug 2016 20:10:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dIF3slg0OfGvUZs3OBLzfNGIdWCfVrLc+HbzYRl6oy8=; b=ZIx9+/QlZ8alOLOBnxzRDiR9lBMrAbN1nWu9vH56oJsSiog6NDMfGZyGwu3XpJeHiu IUPs9T4yi1tNp7C8fDLok30VYlYjm11AkGuOSC7vvXOB4KK0vn3rcRm10LkTVsskO4nJ aZVoqpAUx9PQyfRlBh+2ps9a5jyhOUQ0DPfZn6JKM2aHhhBSSZeLMlsKgrUXtV3gSF4C 8gzvpS46nT7EdDkhHV5ROJJAT7L/GZlRsqXbx/4jJgTOhVxZauy/Upx6OaAyMvKoGWk2 73Eo9uzVJS/kfzjrK27Y2AOdZhc4xGkhKUNtioiXrjATC4/2iPc+oB1AZGtvXKB6afQj 7w8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dIF3slg0OfGvUZs3OBLzfNGIdWCfVrLc+HbzYRl6oy8=; b=VR3R9cu5ec0Lk7Y1csIOcIDKHJb1wQZw9eI8Agvs6YxelMs4b549BU8B2yUcZA9IFW bdc7XGHgNPPvaCS8vS/PUuvPx91AzmsVWuoqac7wnS6/6XC3RACn7fPw9zr0V4u+R+BS /Mgf1yTOvAeM+NuuQfp8pMYucrwvNiMpCrYNVJJc1lpqXQU9IypsCGxYTghQSH334zNK JAdPj0GIx2XBIctjO/hzxhXSHe6vTlOHwHS+zKf6fRhOhqWqcMSZEFvGGZoGQ4tRgS2a ubRuy8dxsg9Gd895DqHTcrdg9PvTfDN2owC6b5SE1MSB3sux1SZul9IJGV/EJZ6Qd4fl CbSg== X-Gm-Message-State: AEkooutU3qk7mUf9wO1StnCwH4jrKlWyY69yJ3KDcV7txfIIct8+/3P/ZzSq5K2W+kyobg== X-Received: by 10.66.249.201 with SMTP id yw9mr95723077pac.130.1470193852641; Tue, 02 Aug 2016 20:10:52 -0700 (PDT) Received: from localhost ([2601:646:8581:937e:fc58:edc5:1254:cc96]) by smtp.gmail.com with ESMTPSA id cf1sm7950559pac.20.2016.08.02.20.10.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Aug 2016 20:10:51 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 2 Aug 2016 20:10:51 -0700 Message-Id: <8cba468d84b0cac244064b10a103a936808c8cef.1470156587.git.alistair@alistair23.me> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2607:f8b0:400e:c03::244 Subject: [Qemu-devel] [PATCH v6 3/8] STM32F2xx: Add the ADC device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, konstanty@ieee.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell --- V4: - Remove the rand() function - Add VMState - Small cleanups V2: - Address Peter C's comments - Create a ADC folder and move the file in there - Move some of the registers into arrays default-configs/arm-softmmu.mak | 1 + hw/Makefile.objs | 1 + hw/adc/Makefile.objs | 1 + hw/adc/stm32f2xx_adc.c | 306 ++++++++++++++++++++++++++++++++++++++++ include/hw/adc/stm32f2xx_adc.h | 87 ++++++++++++ 5 files changed, 396 insertions(+) create mode 100644 hw/adc/Makefile.objs create mode 100644 hw/adc/stm32f2xx_adc.c create mode 100644 include/hw/adc/stm32f2xx_adc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 7a19863..5b1696d 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -87,6 +87,7 @@ CONFIG_ZYNQ=y CONFIG_STM32F2XX_TIMER=y CONFIG_STM32F2XX_USART=y CONFIG_STM32F2XX_SYSCFG=y +CONFIG_STM32F2XX_ADC=y CONFIG_STM32F205_SOC=y CONFIG_VERSATILE_PCI=y diff --git a/hw/Makefile.objs b/hw/Makefile.objs index 4a07ed4..0ffd281 100644 --- a/hw/Makefile.objs +++ b/hw/Makefile.objs @@ -1,5 +1,6 @@ devices-dirs-$(call land, $(CONFIG_VIRTIO),$(call land,$(CONFIG_VIRTFS),$(CONFIG_PCI))) += 9pfs/ devices-dirs-$(CONFIG_ACPI) += acpi/ +devices-dirs-$(CONFIG_SOFTMMU) += adc/ devices-dirs-$(CONFIG_SOFTMMU) += audio/ devices-dirs-$(CONFIG_SOFTMMU) += block/ devices-dirs-$(CONFIG_SOFTMMU) += bt/ diff --git a/hw/adc/Makefile.objs b/hw/adc/Makefile.objs new file mode 100644 index 0000000..3f6dfde --- /dev/null +++ b/hw/adc/Makefile.objs @@ -0,0 +1 @@ +obj-$(CONFIG_STM32F2XX_ADC) += stm32f2xx_adc.o diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c new file mode 100644 index 0000000..90fe9de --- /dev/null +++ b/hw/adc/stm32f2xx_adc.c @@ -0,0 +1,306 @@ +/* + * STM32F2XX ADC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "hw/adc/stm32f2xx_adc.h" + +#ifndef STM_ADC_ERR_DEBUG +#define STM_ADC_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (STM_ADC_ERR_DEBUG >= lvl) { \ + qemu_log("%s: " fmt, __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static void stm32f2xx_adc_reset(DeviceState *dev) +{ + STM32F2XXADCState *s = STM32F2XX_ADC(dev); + + s->adc_sr = 0x00000000; + s->adc_cr1 = 0x00000000; + s->adc_cr2 = 0x00000000; + s->adc_smpr1 = 0x00000000; + s->adc_smpr2 = 0x00000000; + s->adc_jofr[0] = 0x00000000; + s->adc_jofr[1] = 0x00000000; + s->adc_jofr[2] = 0x00000000; + s->adc_jofr[3] = 0x00000000; + s->adc_htr = 0x00000FFF; + s->adc_ltr = 0x00000000; + s->adc_sqr1 = 0x00000000; + s->adc_sqr2 = 0x00000000; + s->adc_sqr3 = 0x00000000; + s->adc_jsqr = 0x00000000; + s->adc_jdr[0] = 0x00000000; + s->adc_jdr[1] = 0x00000000; + s->adc_jdr[2] = 0x00000000; + s->adc_jdr[3] = 0x00000000; + s->adc_dr = 0x00000000; +} + +static uint32_t stm32f2xx_adc_generate_value(STM32F2XXADCState *s) +{ + /* Attempts to fake some ADC values */ + s->adc_dr = s->adc_dr + 7; + + switch ((s->adc_cr1 & ADC_CR1_RES) >> 24) { + case 0: + /* 12-bit */ + s->adc_dr &= 0xFFF; + break; + case 1: + /* 10-bit */ + s->adc_dr &= 0x3FF; + break; + case 2: + /* 8-bit */ + s->adc_dr &= 0xFF; + break; + default: + /* 6-bit */ + s->adc_dr &= 0x3F; + } + + if (s->adc_cr2 & ADC_CR2_ALIGN) { + return (s->adc_dr << 1) & 0xFFF0; + } else { + return s->adc_dr; + } +} + +static uint64_t stm32f2xx_adc_read(void *opaque, hwaddr addr, + unsigned int size) +{ + STM32F2XXADCState *s = opaque; + + DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr); + + if (addr >= ADC_COMMON_ADDRESS) { + qemu_log_mask(LOG_UNIMP, + "%s: ADC Common Register Unsupported\n", __func__); + } + + switch (addr) { + case ADC_SR: + return s->adc_sr; + case ADC_CR1: + return s->adc_cr1; + case ADC_CR2: + return s->adc_cr2 & 0xFFFFFFF; + case ADC_SMPR1: + return s->adc_smpr1; + case ADC_SMPR2: + return s->adc_smpr2; + case ADC_JOFR1: + case ADC_JOFR2: + case ADC_JOFR3: + case ADC_JOFR4: + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + return s->adc_jofr[(addr - ADC_JOFR1) / 4]; + case ADC_HTR: + return s->adc_htr; + case ADC_LTR: + return s->adc_ltr; + case ADC_SQR1: + return s->adc_sqr1; + case ADC_SQR2: + return s->adc_sqr2; + case ADC_SQR3: + return s->adc_sqr3; + case ADC_JSQR: + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + return s->adc_jsqr; + case ADC_JDR1: + case ADC_JDR2: + case ADC_JDR3: + case ADC_JDR4: + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + return s->adc_jdr[(addr - ADC_JDR1) / 4] - + s->adc_jofr[(addr - ADC_JDR1) / 4]; + case ADC_DR: + if ((s->adc_cr2 & ADC_CR2_ADON) && (s->adc_cr2 & ADC_CR2_SWSTART)) { + s->adc_cr2 ^= ADC_CR2_SWSTART; + return stm32f2xx_adc_generate_value(s); + } else { + return 0; + } + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); + } + + return 0; +} + +static void stm32f2xx_adc_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + STM32F2XXADCState *s = opaque; + uint32_t value = (uint32_t) val64; + + DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", + addr, value); + + if (addr >= 0x100) { + qemu_log_mask(LOG_UNIMP, + "%s: ADC Common Register Unsupported\n", __func__); + } + + switch (addr) { + case ADC_SR: + s->adc_sr &= (value & 0x3F); + break; + case ADC_CR1: + s->adc_cr1 = value; + break; + case ADC_CR2: + s->adc_cr2 = value; + break; + case ADC_SMPR1: + s->adc_smpr1 = value; + break; + case ADC_SMPR2: + s->adc_smpr2 = value; + break; + case ADC_JOFR1: + case ADC_JOFR2: + case ADC_JOFR3: + case ADC_JOFR4: + s->adc_jofr[(addr - ADC_JOFR1) / 4] = (value & 0xFFF); + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + break; + case ADC_HTR: + s->adc_htr = value; + break; + case ADC_LTR: + s->adc_ltr = value; + break; + case ADC_SQR1: + s->adc_sqr1 = value; + break; + case ADC_SQR2: + s->adc_sqr2 = value; + break; + case ADC_SQR3: + s->adc_sqr3 = value; + break; + case ADC_JSQR: + s->adc_jsqr = value; + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + break; + case ADC_JDR1: + case ADC_JDR2: + case ADC_JDR3: + case ADC_JDR4: + s->adc_jdr[(addr - ADC_JDR1) / 4] = value; + qemu_log_mask(LOG_UNIMP, "%s: " \ + "Injection ADC is not implemented, the registers are " \ + "included for compatibility\n", __func__); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); + } +} + +static const MemoryRegionOps stm32f2xx_adc_ops = { + .read = stm32f2xx_adc_read, + .write = stm32f2xx_adc_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static const VMStateDescription vmstate_stm32f2xx_adc = { + .name = TYPE_STM32F2XX_ADC, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(adc_sr, STM32F2XXADCState), + VMSTATE_UINT32(adc_cr1, STM32F2XXADCState), + VMSTATE_UINT32(adc_cr2, STM32F2XXADCState), + VMSTATE_UINT32(adc_smpr1, STM32F2XXADCState), + VMSTATE_UINT32(adc_smpr2, STM32F2XXADCState), + VMSTATE_UINT32_ARRAY(adc_jofr, STM32F2XXADCState, 4), + VMSTATE_UINT32(adc_htr, STM32F2XXADCState), + VMSTATE_UINT32(adc_ltr, STM32F2XXADCState), + VMSTATE_UINT32(adc_sqr1, STM32F2XXADCState), + VMSTATE_UINT32(adc_sqr2, STM32F2XXADCState), + VMSTATE_UINT32(adc_sqr3, STM32F2XXADCState), + VMSTATE_UINT32(adc_jsqr, STM32F2XXADCState), + VMSTATE_UINT32_ARRAY(adc_jdr, STM32F2XXADCState, 4), + VMSTATE_UINT32(adc_dr, STM32F2XXADCState), + VMSTATE_END_OF_LIST() + } +}; + +static void stm32f2xx_adc_init(Object *obj) +{ + STM32F2XXADCState *s = STM32F2XX_ADC(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s, + TYPE_STM32F2XX_ADC, 0xFF); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void stm32f2xx_adc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = stm32f2xx_adc_reset; + dc->vmsd = &vmstate_stm32f2xx_adc; +} + +static const TypeInfo stm32f2xx_adc_info = { + .name = TYPE_STM32F2XX_ADC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(STM32F2XXADCState), + .instance_init = stm32f2xx_adc_init, + .class_init = stm32f2xx_adc_class_init, +}; + +static void stm32f2xx_adc_register_types(void) +{ + type_register_static(&stm32f2xx_adc_info); +} + +type_init(stm32f2xx_adc_register_types) diff --git a/include/hw/adc/stm32f2xx_adc.h b/include/hw/adc/stm32f2xx_adc.h new file mode 100644 index 0000000..a72f734 --- /dev/null +++ b/include/hw/adc/stm32f2xx_adc.h @@ -0,0 +1,87 @@ +/* + * STM32F2XX ADC + * + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_STM32F2XX_ADC_H +#define HW_STM32F2XX_ADC_H + +#define ADC_SR 0x00 +#define ADC_CR1 0x04 +#define ADC_CR2 0x08 +#define ADC_SMPR1 0x0C +#define ADC_SMPR2 0x10 +#define ADC_JOFR1 0x14 +#define ADC_JOFR2 0x18 +#define ADC_JOFR3 0x1C +#define ADC_JOFR4 0x20 +#define ADC_HTR 0x24 +#define ADC_LTR 0x28 +#define ADC_SQR1 0x2C +#define ADC_SQR2 0x30 +#define ADC_SQR3 0x34 +#define ADC_JSQR 0x38 +#define ADC_JDR1 0x3C +#define ADC_JDR2 0x40 +#define ADC_JDR3 0x44 +#define ADC_JDR4 0x48 +#define ADC_DR 0x4C + +#define ADC_CR2_ADON 0x01 +#define ADC_CR2_CONT 0x02 +#define ADC_CR2_ALIGN 0x800 +#define ADC_CR2_SWSTART 0x40000000 + +#define ADC_CR1_RES 0x3000000 + +#define ADC_COMMON_ADDRESS 0x100 + +#define TYPE_STM32F2XX_ADC "stm32f2xx-adc" +#define STM32F2XX_ADC(obj) \ + OBJECT_CHECK(STM32F2XXADCState, (obj), TYPE_STM32F2XX_ADC) + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + + uint32_t adc_sr; + uint32_t adc_cr1; + uint32_t adc_cr2; + uint32_t adc_smpr1; + uint32_t adc_smpr2; + uint32_t adc_jofr[4]; + uint32_t adc_htr; + uint32_t adc_ltr; + uint32_t adc_sqr1; + uint32_t adc_sqr2; + uint32_t adc_sqr3; + uint32_t adc_jsqr; + uint32_t adc_jdr[4]; + uint32_t adc_dr; + + qemu_irq irq; +} STM32F2XXADCState; + +#endif /* HW_STM32F2XX_ADC_H */