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[RS6000] power8 unaligned fp load/store

Message ID 20160802143732.GH20904@bubble.grove.modra.org
State New
Headers show

Commit Message

Alan Modra Aug. 2, 2016, 2:37 p.m. UTC 
According to the POWER8 Processor User’s Manual and some
experimentation on power8 hardware, unaligned fp load/store on power8
does not invoke the alignment interrupt.  Thus SLOW_UNALIGNED_ACCESS
should not return true for these accesses.  It so happens that we
already have an undocumented switch to control whether VSX vector
access is slow, and since FPRs are a subset of VSX regs it seemed good
to me to use the same switch.

Bootstrapped and regtested powerpc64le-linux and powerpc64-linux.

	* config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Make scalar
	float access depend on TARGET_EFFICIENT_UNALIGNED_VSX.
	* config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Renamed
	from -mefficient-unaligned-vector.  Note that this affects fp too.

Comments

Segher Boessenkool Aug. 2, 2016, 6:02 p.m. UTC | #1 
On Wed, Aug 03, 2016 at 12:07:32AM +0930, Alan Modra wrote:
> According to the POWER8 Processor User’s Manual and some
> experimentation on power8 hardware, unaligned fp load/store on power8
> does not invoke the alignment interrupt.  Thus SLOW_UNALIGNED_ACCESS
> should not return true for these accesses.  It so happens that we
> already have an undocumented switch to control whether VSX vector
> access is slow, and since FPRs are a subset of VSX regs it seemed good
> to me to use the same switch.

Okay for trunk, thanks!


Segher
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9b3e83b..af77258 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -990,10 +990,10 @@  enum data_align { align_abi, align_opt, align_both };
    aligned to 4 or 8 bytes.  */
 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN)				\
   (STRICT_ALIGNMENT							\
-   || (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) && (ALIGN) < 32)		\
-   || (!TARGET_EFFICIENT_UNALIGNED_VSX                                  \
-       && ((VECTOR_MODE_P (MODE) || FLOAT128_VECTOR_P (MODE))		\
-	   && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))))
+   || (!TARGET_EFFICIENT_UNALIGNED_VSX					\
+       && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) && (ALIGN) < 32)	\
+	   || ((VECTOR_MODE_P (MODE) || FLOAT128_VECTOR_P (MODE))	\
+	       && (int) (ALIGN) < VECTOR_ALIGN (MODE)))))
 
 
 /* Standard register usage.  */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 9e9d33e..e47f47f 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -211,9 +211,9 @@  mallow-movmisalign
 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
 ; Allow the movmisalign in DF/DI vectors
 
-mefficient-unaligned-vector
+mefficient-unaligned-vsx
 Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
-; Consider unaligned VSX accesses to be efficient
+; Consider unaligned VSX vector and fp accesses to be efficient
 
 mallow-df-permute
 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save