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[U-Boot] timing_cfg_2 register in FSL DDR driver

Message ID 1BBC30BFBAE48D49A8C663EE5D39C03F01B7F0C2F8@SDEMUCMB02.kontron.local
State Accepted
Commit 8936691ba69bc322201c62e977e2803cfe67fc40
Headers show

Commit Message

Thomas Schaefer July 29, 2016, 3:18 p.m. UTC 
Hi York,

with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better to set wr_lat this way


Best regards,
Thomas

Comments

York Sun July 29, 2016, 3:52 p.m. UTC | #1 
On 07/29/2016 08:19 AM, Thomas Schaefer wrote:
> Hi York,
>
> with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better to set wr_lat this way
>
> diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
> index 1d5cec6..5840b9d 100644
> --- a/drivers/ddr/fsl/ctrl_regs.c
> +++ b/drivers/ddr/fsl/ctrl_regs.c
> @@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
>  		| ((add_lat_mclk & 0xf) << 28)
>  		| ((cpo & 0x1f) << 23)
>  		| ((wr_lat & 0xf) << 19)
> -		| ((wr_lat & 0x10) << 18)
> +		| (((wr_lat & 0x10) >> 4) << 18)
>  		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
>  		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
>  		| ((cke_pls & 0x7) << 6)
>

Thomas,

Thanks for finding this error.

York
diff mbox

Patch

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 1d5cec6..5840b9d 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@  static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 18)
+		| (((wr_lat & 0x10) >> 4) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)