===================================================================
@@ -35,10 +35,10 @@ (define_register_constraint "d" "(TARGET
;; In the non-V9 case, coerce V9 'e' class to 'f', so we can use 'e' in the
;; MD file for V8 and V9.
-(define_register_constraint "e" "TARGET_V9 ? EXTRA_FP_REGS : FP_REGS"
+(define_register_constraint "e" "(TARGET_FPU ? (TARGET_V9 ? EXTRA_FP_REGS : FP_REGS) : NO_REGS)"
"Any floating-point register")
-(define_register_constraint "f" "FP_REGS"
+(define_register_constraint "f" "(TARGET_FPU ? FP_REGS : NO_REGS)"
"Lower floating-point register")
(define_register_constraint "h" "(TARGET_V9 && TARGET_V8PLUS ? I64_REGS : NO_REGS)"
This is an ICE compiling the kernel with -mno-fpu on the SPARC. reload aborts because it is unable to find a register to spill in class 'FP_REGS', which is paradoxical since the insn involves integer values only: (insn 166 123 140 4 /home/ebotcazou/src-4.4/gcc/testsuite/gcc.target/sparc/pr35664.c:82 (set (reg:DI 262 [ <variable>.stats.ptc1522 ]) (mem/s:DI (plus:SI (reg/v/f:SI 24 %i0 [orig:121 adapter ] [121]) (reg:SI 4 %g4 [244])) [14 <variable>.stats.ptc1522+0 S8 A64])) 45 {*movdi_insn_sp32} (expr_list:REG_EQUIV (mem/s:DI (plus:SI (reg/v/f:SI 24 %i0 [orig:121 adapter ] [121]) (reg:SI 4 %g4 [244])) [14 <variable>.stats.ptc1522+0 S8 A64]) (nil))) and -mno-fpu is used. It turns out that reload will really choose an FP reg as a reload register in this case (DImode load with non-offsetable address) if -mno-fpu isn't specified, before eliminating it thanks to the REG_EQUIV. Fixed by making constraints 'e' and 'f' return NO_REGS if -mno-fpu is used. Tested on SPARC64/Linux and SPARC/Solaris, applied on mainline and 4.5/4.4 branches. 2010-09-22 Eric Botcazou <ebotcazou@adacore.com> PR target/35664 * config/sparc/constraints.md ('e'): Return NO_REGS if !TARGET_FPU. ('f'): Likewise. 2010-09-22 Eric Botcazou <ebotcazou@adacore.com> * gcc.target/sparc/mnofpu.c: New test.