From patchwork Tue Sep 21 13:15:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Schmidt X-Patchwork-Id: 65306 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 09F71B70AB for ; Tue, 21 Sep 2010 23:14:38 +1000 (EST) Received: (qmail 5058 invoked by alias); 21 Sep 2010 13:14:36 -0000 Received: (qmail 4974 invoked by uid 22791); 21 Sep 2010 13:14:35 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Tue, 21 Sep 2010 13:14:31 +0000 Received: (qmail 12759 invoked from network); 21 Sep 2010 13:14:28 -0000 Received: from unknown (HELO ?84.152.245.156?) (bernds@127.0.0.2) by mail.codesourcery.com with ESMTPA; 21 Sep 2010 13:14:28 -0000 Message-ID: <4C98AFDC.70805@codesourcery.com> Date: Tue, 21 Sep 2010 15:15:08 +0200 From: Bernd Schmidt User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.9) Gecko/20100911 Lightning/1.0b3pre Thunderbird/3.1.3 MIME-Version: 1.0 To: Richard Earnshaw CC: GCC Patches Subject: Re: ARM: More reorganization of extend patterns (PR43137) References: <4C3C383E.8060604@codesourcery.com> <1283356334.19320.2.camel@e102346-lin.cambridge.arm.com> <4C914925.1030003@codesourcery.com> <1284631462.324.30.camel@e102346-lin.cambridge.arm.com> In-Reply-To: <1284631462.324.30.camel@e102346-lin.cambridge.arm.com> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On 09/16/2010 12:04 PM, Richard Earnshaw wrote: > So as Uros points out, the constraints also need a macro substitution > (or you'll end up with a potentially invalid insn during reload). > > Otherwise, OK. Here's the patch I committed. Bernd Index: config/arm/iterators.md =================================================================== --- config/arm/iterators.md (revision 164476) +++ config/arm/iterators.md (working copy) @@ -381,6 +381,10 @@ (define_mode_attr V_unpack [(V16QI "V8 (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "&& arm_arch6")]) +(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") + (HI "nonimmediate_operand") + (QI "nonimmediate_operand")]) +(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")]) ;;---------------------------------------------------------------------------- ;; Code attributes Index: config/arm/arm.md =================================================================== --- config/arm/arm.md (revision 164476) +++ config/arm/arm.md (working copy) @@ -4042,7 +4042,8 @@ (define_expand "truncdfhf2" (define_insn "zero_extenddi2" [(set (match_operand:DI 0 "s_register_operand" "=r") - (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] + (zero_extend:DI (match_operand:QHSI 1 "" + "")))] "TARGET_32BIT " "#" [(set_attr "length" "8") @@ -4052,7 +4053,8 @@ (define_insn "zero_extenddi2" (define_insn "extenddi2" [(set (match_operand:DI 0 "s_register_operand" "=r") - (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] + (sign_extend:DI (match_operand:QHSI 1 "" + "")))] "TARGET_32BIT " "#" [(set_attr "length" "8")