| Message ID | 1469527429-15065-1-git-send-email-jh80.chung@samsung.com |
|---|---|
| State | Accepted |
| Commit | e1ea7c44d67dde263c13e1aef300cab408236994 |
| Delegated to: | Jaehoon Chung |
| Headers | show |
Hi All, On 07/26/2016 07:03 PM, Jaehoon Chung wrote: > This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. > SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. > > For example, Exynos didn't have CTRL_HISPD. But Highspeed mode > is supported. > (This quirks doesn't mean that driver didn't support the Highseepd mode.) > > Note: If driver didn't support the Highspeed Mode, use or add the other > quirks. > > After applied this patch, all Exynos SoCs are just running with 25MHz. SDHCI_QUIRK_NO_HISPD had added from me. At that time, it meant the Controller doesn't have the SDHCI_CTRL_HISPD bit[2]. In exynos, this bit is using as OUTEDGINV (Output Egde Inversion). I added SDHCI_QUIRK_NO_HISPD to prevent wrong bit operation likes this. And in drivers/mmc/mmc.c 1328 line, mmc->card_caps &= mmc->cfg->host_caps; After reading card's capabilities, if card didn't support those, then it's cleared. I don't know why cleared these capabilities before checking the card's capabilities. After applied commit "42979002602" Device: SAMSUNG SDHCI Manufacturer ID: 3 OEM: 5344 Name: SU16G Tran Speed: 25000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes After reverted commit "42979002602" Device: SAMSUNG SDHCI Manufacturer ID: 3 OEM: 5344 Name: SU16G Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.8 GiB Bus Width: 4-bit Erase Group Size: 512 Bytes There is no purpose, it needs to revert for Other SoCs. Best Regards, Jaehoon Chung > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > --- > drivers/mmc/sdhci.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c > index 9fdbed8..1fa4038 100644 > --- a/drivers/mmc/sdhci.c > +++ b/drivers/mmc/sdhci.c > @@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, > cfg->host_caps |= MMC_MODE_8BIT; > } > > - if (quirks & SDHCI_QUIRK_NO_HISPD_BIT) > - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); > - > if (host_caps) > cfg->host_caps |= host_caps; > >
On 07/26/2016 07:03 PM, Jaehoon Chung wrote: > This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. > SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. > > For example, Exynos didn't have CTRL_HISPD. But Highspeed mode > is supported. > (This quirks doesn't mean that driver didn't support the Highseepd mode.) > > Note: If driver didn't support the Highspeed Mode, use or add the other > quirks. > > After applied this patch, all Exynos SoCs are just running with 25MHz. Applied on u-boot-mmc. Best Regards, Jaehoon Chung > > Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> > --- > drivers/mmc/sdhci.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c > index 9fdbed8..1fa4038 100644 > --- a/drivers/mmc/sdhci.c > +++ b/drivers/mmc/sdhci.c > @@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, > cfg->host_caps |= MMC_MODE_8BIT; > } > > - if (quirks & SDHCI_QUIRK_NO_HISPD_BIT) > - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); > - > if (host_caps) > cfg->host_caps |= host_caps; > >
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 9fdbed8..1fa4038 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, cfg->host_caps |= MMC_MODE_8BIT; } - if (quirks & SDHCI_QUIRK_NO_HISPD_BIT) - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); - if (host_caps) cfg->host_caps |= host_caps;
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit. For example, Exynos didn't have CTRL_HISPD. But Highspeed mode is supported. (This quirks doesn't mean that driver didn't support the Highseepd mode.) Note: If driver didn't support the Highspeed Mode, use or add the other quirks. After applied this patch, all Exynos SoCs are just running with 25MHz. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> --- drivers/mmc/sdhci.c | 3 --- 1 file changed, 3 deletions(-)