diff mbox

[v3,07/15] target-ppc: implement branch-less divw[o][.]

Message ID 1469467240-21273-8-git-send-email-nikunj@linux.vnet.ibm.com
State New
Headers show

Commit Message

Nikunj A Dadhania July 25, 2016, 5:20 p.m. UTC 
While implementing modulo instructions figured out that the
implementation uses many branches. Change the logic to achieve the
branch-less code. Undefined value is set to dividend in case of invalid
input.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate.c | 48 +++++++++++++++++++++++-------------------------
 1 file changed, 23 insertions(+), 25 deletions(-)

Comments

Richard Henderson July 26, 2016, 12:17 a.m. UTC | #1 
On 07/25/2016 10:50 PM, Nikunj A Dadhania wrote:
>      if (compute_ov) {
> -        tcg_gen_movi_tl(cpu_ov, 1);
> -        tcg_gen_movi_tl(cpu_so, 1);
> +        tcg_gen_extu_i32_tl(cpu_ov, t2);
> +        tcg_gen_extu_i32_tl(cpu_so, t2);
>      }

This should be

   tcg_gen_extu_i32_tl(cpu_ov, t2);
   tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);

I.e. the summary overflow accumulates.


r~
Nikunj A Dadhania July 26, 2016, 1:52 a.m. UTC | #2 
Richard Henderson <rth@twiddle.net> writes:

> On 07/25/2016 10:50 PM, Nikunj A Dadhania wrote:
>>      if (compute_ov) {
>> -        tcg_gen_movi_tl(cpu_ov, 1);
>> -        tcg_gen_movi_tl(cpu_so, 1);
>> +        tcg_gen_extu_i32_tl(cpu_ov, t2);
>> +        tcg_gen_extu_i32_tl(cpu_so, t2);
>>      }
>
> This should be
>
>    tcg_gen_extu_i32_tl(cpu_ov, t2);
>    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
>
> I.e. the summary overflow accumulates.

Sure, i missed that bit. In the previous case it was always setting it
to 1, because an overflow had occurred. And not changing it otherwise. 

Regards
Nikunj
diff mbox

Patch

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7c7328f..c77b826 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1049,41 +1049,39 @@  static void gen_addpcis(DisasContext *ctx)
 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
                                      TCGv arg2, int sign, int compute_ov)
 {
-    TCGLabel *l1 = gen_new_label();
-    TCGLabel *l2 = gen_new_label();
-    TCGv_i32 t0 = tcg_temp_local_new_i32();
-    TCGv_i32 t1 = tcg_temp_local_new_i32();
+    TCGv_i32 t0 = tcg_temp_new_i32();
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+    TCGv_i32 t3 = tcg_temp_new_i32();
 
     tcg_gen_trunc_tl_i32(t0, arg1);
     tcg_gen_trunc_tl_i32(t1, arg2);
-    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
-    if (sign) {
-        TCGLabel *l3 = gen_new_label();
-        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
-        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
-        gen_set_label(l3);
-        tcg_gen_div_i32(t0, t0, t1);
-    } else {
-        tcg_gen_divu_i32(t0, t0, t1);
-    }
-    if (compute_ov) {
-        tcg_gen_movi_tl(cpu_ov, 0);
-    }
-    tcg_gen_br(l2);
-    gen_set_label(l1);
     if (sign) {
-        tcg_gen_sari_i32(t0, t0, 31);
+        tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
+        tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
+        tcg_gen_and_i32(t2, t2, t3);
+        tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
+        tcg_gen_or_i32(t2, t2, t3);
+        tcg_gen_movi_i32(t3, 0);
+        tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
+        tcg_gen_div_i32(t3, t0, t1);
+        tcg_gen_extu_i32_tl(ret, t3);
     } else {
-        tcg_gen_movi_i32(t0, 0);
+        tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
+        tcg_gen_movi_i32(t3, 0);
+        tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
+        tcg_gen_divu_i32(t3, t0, t1);
+        tcg_gen_extu_i32_tl(ret, t3);
     }
     if (compute_ov) {
-        tcg_gen_movi_tl(cpu_ov, 1);
-        tcg_gen_movi_tl(cpu_so, 1);
+        tcg_gen_extu_i32_tl(cpu_ov, t2);
+        tcg_gen_extu_i32_tl(cpu_so, t2);
     }
-    gen_set_label(l2);
-    tcg_gen_extu_i32_tl(ret, t0);
     tcg_temp_free_i32(t0);
     tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+    tcg_temp_free_i32(t3);
+
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx, ret);
 }