Message ID | 20160725101547.18503-2-vigneshr@ti.com |
---|---|
State | Accepted |
Commit | 4d790788ce009909842290e85d3e57db36935ad4 |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
On Mon, Jul 25, 2016 at 03:45:44PM +0530, Vignesh R wrote: > From: Lokesh Vutla <lokeshvutla@ti.com> > > According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence > update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz > clock, so that driver can use the same. > > Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
On Monday 25 July 2016 03:45 PM, Vignesh R wrote: > From: Lokesh Vutla <lokeshvutla@ti.com> > > According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence > update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz > clock, so that driver can use the same. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > --- Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Regards Mugunthan V N
On 29 July 2016 at 14:12, Mugunthan V N <mugunthanvnm@ti.com> wrote: > On Monday 25 July 2016 03:45 PM, Vignesh R wrote: >> From: Lokesh Vutla <lokeshvutla@ti.com> >> >> According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence >> update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz >> clock, so that driver can use the same. >> >> Signed-off-by: Vignesh R <vigneshr@ti.com> >> --- > > Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 62dd275f7ee8..a83f68c366a0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -160,7 +160,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ - {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */