From patchwork Mon Sep 20 16:24:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Earnshaw X-Patchwork-Id: 65221 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 3C2A4B70A7 for ; Tue, 21 Sep 2010 02:25:06 +1000 (EST) Received: (qmail 26117 invoked by alias); 20 Sep 2010 16:25:04 -0000 Received: (qmail 26097 invoked by uid 22791); 20 Sep 2010 16:25:03 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (217.140.96.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 20 Sep 2010 16:24:58 +0000 Received: from cam-owa1.Emea.Arm.com (cam-owa1.emea.arm.com [10.1.255.62]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id o8KGMEF9027704; Mon, 20 Sep 2010 17:22:15 +0100 (BST) Received: from [10.1.67.34] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 20 Sep 2010 17:24:55 +0100 Subject: Re: [ARM][PATCH] Fix PR 45726: invalid instruction on arm9tdmi. From: Richard Earnshaw To: gcc patches Cc: rafael.carre@gmail.com In-Reply-To: <1284996945.13878.28.camel@e102346-lin.cambridge.arm.com> References: <1284996945.13878.28.camel@e102346-lin.cambridge.arm.com> Date: Mon, 20 Sep 2010 17:24:54 +0100 Message-Id: <1284999894.13878.43.camel@e102346-lin.cambridge.arm.com> Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Mon, 2010-09-20 at 16:35 +0100, Richard Earnshaw wrote: > PR 45726 is a wrong code bug on ARM where we accidentally emit an > instruction to perform a bitfield-insert-immediate on machines with no > support for MOVT. The patch is pretty trivial, we just disable the > pattern on machines without MOVT. > > Committed to 4.5 branch and trunk. > > R. > > 2010-09-20 Rafael Carre > > PR target/45726 > * arm.md (arm_movtas_ze): Only enable on machine with MOVT. I missed a second part to this patch. There's another instruction pattern that is incorrectly enabled for all 32-bit compiles: arm_movt. I think in this case the compiler will never end up generating this pattern spontaneously, so for the moment I've only committed this to trunk. 2010-09-20 Rafael Carre PR target/45726 * arm.md (arm_movt): Only enable on machines with MOVT. Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 164440) +++ gcc/config/arm/arm.md (working copy) @@ -5119,7 +5119,7 @@ (define_insn "*arm_movt" [(set (match_operand:SI 0 "nonimmediate_operand" "=r") (lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "general_operand" "i")))] - "TARGET_32BIT" + "arm_arch_thumb2" "movt%?\t%0, #:upper16:%c2" [(set_attr "predicable" "yes") (set_attr "length" "4")]